OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sym/] [cde_jtag_tap_logic.sym] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  4700 4700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 4850   5 10 1 1 0 0 1 1
4 
device=cde_jtag_tap_logic
5 
T 400 5050 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 5200    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 5200    0 10 0 1 0 0 1 1
10 
library=cde
11 
T 400 5200    0 10 0 1 0 0 1 1
12 
component=jtag
13 
T 400 5200    0 10 0 1 0 0 1 1
14 
version=tap_logic
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=instruction[3:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 4 0 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=update_dr_o
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 4 0 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=update_dr_clk_o
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 4 0 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=test_logic_reset_o
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 4 0 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=tdo_i
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=tdi_pad_in
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=shift_dr_o
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
67 
pinnumber=jtag_shift_clk
68 
T 400 1600 5 10 0 1 0 1 1 1
69 
pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
72 
{
73 
T 400 1800 5 10 1 1 0 1 1 1
74 
pinnumber=chip_id_tdo
75 
T 400 1800 5 10 0 1 0 1 1 1
76 
pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
79 
{
80 
T 400 2000 5 10 1 1 0 1 1 1
81 
pinnumber=capture_dr_o
82 
T 400 2000 5 10 0 1 0 1 1 1
83 
pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
86 
{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=aux_tdo_i
89 
T 400 2200 5 10 0 1 0 1 1 1
90 
pinseq=11
91 
}
92 
P 5000 200 5300 200 10 1 1
93 
{
94 
T 4900 200 5  10 1 1 0 7 1 1
95 
pinnumber=chip_id_value[31:0]
96 
T 4900 200 5  10 0 1 0 7 1 1
97 
pinseq=12
98 
}
99 
P 5000 400 5300 400 4 0 1
100 
{
101 
T 4900 400 5  10 1 1 0 7 1 1
102 
pinnumber=tdi_o
103 
T 5000 400 5  10 0 1 0 7 1 1
104 
pinseq=13
105 
}
106 
P 5000 600 5300 600 4 0 1
107 
{
108 
T 4900 600 5  10 1 1 0 7 1 1
109 
pinnumber=shiftcapture_dr_o
110 
T 5000 600 5  10 0 1 0 7 1 1
111 
pinseq=14
112 
}
113 
P 5000 800 5300 800 4 0 1
114 
{
115 
T 4900 800 5  10 1 1 0 7 1 1
116 
pinnumber=shiftcapture_dr_clk_o
117 
T 5000 800 5  10 0 1 0 7 1 1
118 
pinseq=15
119 
}
120 
P 5000 1000 5300 1000 4 0 1
121 
{
122 
T 4900 1000 5  10 1 1 0 7 1 1
123 
pinnumber=select_o
124 
T 5000 1000 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 5000 1200 5300 1200 4 0 1
128 
{
129 
T 4900 1200 5  10 1 1 0 7 1 1
130 
pinnumber=sample
131 
T 5000 1200 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 5000 1400 5300 1400 4 0 1
135 
{
136 
T 4900 1400 5  10 1 1 0 7 1 1
137 
pinnumber=next_tdo
138 
T 5000 1400 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 5000 1600 5300 1600 4 0 1
142 
{
143 
T 4900 1600 5  10 1 1 0 7 1 1
144 
pinnumber=jtag_reset
145 
T 5000 1600 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 5000 1800 5300 1800 4 0 1
149 
{
150 
T 4900 1800 5  10 1 1 0 7 1 1
151 
pinnumber=jtag_clk
152 
T 5000 1800 5  10 0 1 0 7 1 1
153 
pinseq=20
154 
}
155 
P 5000 2000 5300 2000 4 0 1
156 
{
157 
T 4900 2000 5  10 1 1 0 7 1 1
158 
pinnumber=extest
159 
T 5000 2000 5  10 0 1 0 7 1 1
160 
pinseq=21
161 
}
162 
P 5000 2200 5300 2200 4 0 1
163 
{
164 
T 4900 2200 5  10 1 1 0 7 1 1
165 
pinnumber=clamp
166 
T 5000 2200 5  10 0 1 0 7 1 1
167 
pinseq=22
168 
}
169 
P 5000 2400 5300 2400 4 0 1
170 
{
171 
T 4900 2400 5  10 1 1 0 7 1 1
172 
pinnumber=chip_id_select
173 
T 5000 2400 5  10 0 1 0 7 1 1
174 
pinseq=23
175 
}
176 
P 5000 2600 5300 2600 4 0 1
177 
{
178 
T 4900 2600 5  10 1 1 0 7 1 1
179 
pinnumber=bsr_select_o
180 
T 5000 2600 5  10 0 1 0 7 1 1
181 
pinseq=24
182 
}
183 
P 5000 2800 5300 2800 4 0 1
184 
{
185 
T 4900 2800 5  10 1 1 0 7 1 1
186 
pinnumber=aux_update_dr_o
187 
T 5000 2800 5  10 0 1 0 7 1 1
188 
pinseq=25
189 
}
190 
P 5000 3000 5300 3000 4 0 1
191 
{
192 
T 4900 3000 5  10 1 1 0 7 1 1
193 
pinnumber=aux_update_dr_clk_o
194 
T 5000 3000 5  10 0 1 0 7 1 1
195 
pinseq=26
196 
}
197 
P 5000 3200 5300 3200 4 0 1
198 
{
199 
T 4900 3200 5  10 1 1 0 7 1 1
200 
pinnumber=aux_test_logic_reset_o
201 
T 5000 3200 5  10 0 1 0 7 1 1
202 
pinseq=27
203 
}
204 
P 5000 3400 5300 3400 4 0 1
205 
{
206 
T 4900 3400 5  10 1 1 0 7 1 1
207 
pinnumber=aux_tdi_o
208 
T 5000 3400 5  10 0 1 0 7 1 1
209 
pinseq=28
210 
}
211 
P 5000 3600 5300 3600 4 0 1
212 
{
213 
T 4900 3600 5  10 1 1 0 7 1 1
214 
pinnumber=aux_shiftcapture_dr_clk_o
215 
T 5000 3600 5  10 0 1 0 7 1 1
216 
pinseq=29
217 
}
218 
P 5000 3800 5300 3800 4 0 1
219 
{
220 
T 4900 3800 5  10 1 1 0 7 1 1
221 
pinnumber=aux_shift_dr_o
222 
T 5000 3800 5  10 0 1 0 7 1 1
223 
pinseq=30
224 
}
225 
P 5000 4000 5300 4000 4 0 1
226 
{
227 
T 4900 4000 5  10 1 1 0 7 1 1
228 
pinnumber=aux_select_o
229 
T 5000 4000 5  10 0 1 0 7 1 1
230 
pinseq=31
231 
}
232 
P 5000 4200 5300 4200 4 0 1
233 
{
234 
T 4900 4200 5  10 1 1 0 7 1 1
235 
pinnumber=aux_jtag_clk
236 
T 5000 4200 5  10 0 1 0 7 1 1
237 
pinseq=32
238 
}
239 
P 5000 4400 5300 4400 4 0 1
240 
{
241 
T 4900 4400 5  10 1 1 0 7 1 1
242 
pinnumber=aux_capture_dr_o
243 
T 5000 4400 5  10 0 1 0 7 1 1
244 
pinseq=33
245 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.