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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [tap_sm] - Blame information for rev 135

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//********************************************************************
//***
//********************************************************************
 
reg     [ 3 :  0]          next_tap_state;
reg     [ 3 :  0]          tap_state;
reg                        bypass_tdo;
reg                        capture_ir;
reg                        next_tdo;
reg                        shift_ir;
reg                        update_ir;
 
 
 
 
 
 
 
 
 
assign jtag_reset  = ! trst_n_pad_in;
 
//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
 
// TAP state parameters
localparam TEST_LOGIC_RESET = 4'b1111,
           RUN_TEST_IDLE    = 4'b1100,
           SELECT_DR_SCAN   = 4'b0111,
           CAPTURE_DR       = 4'b0110,
           SHIFT_DR         = 4'b0010,
           EXIT1_DR         = 4'b0001,
           PAUSE_DR         = 4'b0011,
           EXIT2_DR         = 4'b0000,
           UPDATE_DR        = 4'b0101,
           SELECT_IR_SCAN   = 4'b0100,
           CAPTURE_IR       = 4'b1110,
           SHIFT_IR         = 4'b1010,
           EXIT1_IR         = 4'b1001,
           PAUSE_IR         = 4'b1011,
           EXIT2_IR         = 4'b1000,
           UPDATE_IR        = 4'b1101;
 
 
 
// next state decode for tap controller
always @(*)
    case (tap_state)    // synopsys parallel_case
      TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
      RUN_TEST_IDLE:    next_tap_state = tms_pad_in ? SELECT_DR_SCAN   : RUN_TEST_IDLE;
      SELECT_DR_SCAN:   next_tap_state = tms_pad_in ? SELECT_IR_SCAN   : CAPTURE_DR;
      CAPTURE_DR:       next_tap_state = tms_pad_in ? EXIT1_DR         : SHIFT_DR;
      SHIFT_DR:         next_tap_state = tms_pad_in ? EXIT1_DR         : SHIFT_DR;
      EXIT1_DR:         next_tap_state = tms_pad_in ? UPDATE_DR        : PAUSE_DR;
      PAUSE_DR:         next_tap_state = tms_pad_in ? EXIT2_DR         : PAUSE_DR;
      EXIT2_DR:         next_tap_state = tms_pad_in ? UPDATE_DR        : SHIFT_DR;
      UPDATE_DR:        next_tap_state = tms_pad_in ? SELECT_DR_SCAN   : RUN_TEST_IDLE;
      SELECT_IR_SCAN:   next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;
      CAPTURE_IR:       next_tap_state = tms_pad_in ? EXIT1_IR         : SHIFT_IR;
      SHIFT_IR:         next_tap_state = tms_pad_in ? EXIT1_IR         : SHIFT_IR;
      EXIT1_IR:         next_tap_state = tms_pad_in ? UPDATE_IR        : PAUSE_IR;
      PAUSE_IR:         next_tap_state = tms_pad_in ? EXIT2_IR         : PAUSE_IR;
      EXIT2_IR:         next_tap_state = tms_pad_in ? UPDATE_IR        : SHIFT_IR;
      UPDATE_IR:        next_tap_state = tms_pad_in ? SELECT_DR_SCAN   : RUN_TEST_IDLE;
    endcase
 
 
//********************************************************************
//*** TAP Controller State Machine Register
//********************************************************************
 
 
always @(posedge clk or negedge trst_n_pad_in)
  if (!trst_n_pad_in)     tap_state  <= TEST_LOGIC_RESET;
  else                    tap_state  <= next_tap_state;
 
 
 
 always @(*)
   begin
   shift_ir     = (tap_state == SHIFT_IR);
   shift_dr_o   = (tap_state == SHIFT_DR);
   update_ir    = (tap_state == UPDATE_IR);
   update_dr_o  = (tap_state == UPDATE_DR);
   capture_dr_o = (tap_state == CAPTURE_DR);
   capture_ir   = (tap_state == CAPTURE_IR);
  end
 
 
 
 
//******************************************************
//*** Instruction Register
//******************************************************
 
reg     [INST_LENGTH-1:0]      instruction_buffer;
 
 
// buffer the instruction register while shifting
 
always @(posedge clk or negedge trst_n_pad_in)
  if (!trst_n_pad_in)          instruction_buffer <= INST_RESET;
  else
  if (capture_ir)              instruction_buffer <= INST_RETURN;
  else
  if (shift_ir)                instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};
 
always @(posedge clk  or negedge trst_n_pad_in)
  if (!trst_n_pad_in)                   instruction <= INST_RESET;
  else
  if (tap_state == TEST_LOGIC_RESET)    instruction <= INST_RESET;
  else
  if (update_ir)                        instruction <= instruction_buffer;
 
 
 
//**********************************************************
// Decode tap_state to get test_logic_reset  signal
//**********************************************************
 
 
 
 
always @(posedge clk  or negedge trst_n_pad_in)
if (!trst_n_pad_in)                        test_logic_reset_o   <= 1'b1;
else
if (next_tap_state == TEST_LOGIC_RESET)    test_logic_reset_o   <= 1'b1;
else                                       test_logic_reset_o   <= 1'b0;
 
 
 
 
//**********************************************************
//** Boundary scan control signals
//**********************************************************
 
 
 
always @(posedge clk  or negedge trst_n_pad_in)
  if (!trst_n_pad_in)                             bsr_output_mode <= 1'b0;
  else
  if (tap_state == TEST_LOGIC_RESET)       bsr_output_mode <= 1'b0;
  else
  if (update_ir)                           bsr_output_mode <=    (instruction_buffer  == EXTEST) || (instruction_buffer  == CLAMP);
 
 
 
//**********************************************************
//**  Control chip pads when we are in highz_mode
//**********************************************************
 
 
 
always @(posedge clk  or negedge trst_n_pad_in)
  if (!trst_n_pad_in)                                 tap_highz_mode <= 1'b0;
  else if (tap_state == TEST_LOGIC_RESET)      tap_highz_mode <= 1'b0;
  else if (update_ir)                          tap_highz_mode <= (instruction_buffer  == HIGHZ_MODE);
 
 
 
 
 
 
//**********************************************************
//*** Bypass register
//**********************************************************
 
always @(posedge clk or negedge trst_n_pad_in)
  if (!trst_n_pad_in)         bypass_tdo <= 1'b0;
  else
  if (capture_dr_o)           bypass_tdo <= 1'b0;
  else
  if (shift_dr_o)             bypass_tdo <= tdi_pad_in;
  else                        bypass_tdo <= bypass_tdo;
 
 
//****************************************************************
//*** Choose what goes out on the TDO pin
//****************************************************************
// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode
 
wire bypass_select;
 
assign   bypass_select  = ( instruction == CLAMP ) || ( instruction == BYPASS );
 
 
// output the instruction register when tap_state[3] is 1, else
//   put out the appropriate data register.
 
 
 
 
always@(*)
  begin
     if( tap_state[3] )    next_tdo =  instruction_buffer[0];
     else
     if(bypass_select)     next_tdo =  bypass_tdo;
     else                  next_tdo =  tdo_in;
  end
 
wire   clk_n;
assign clk_n = ! clk;
 
 
always @(posedge clk_n or negedge trst_n_pad_in)
        if (!trst_n_pad_in)         tdo_pad_out <= 1'b0;
        else                        tdo_pad_out <= next_tdo;
 
 
 
// output enable for TDO pad
 
always @(posedge clk_n or negedge trst_n_pad_in)
        if ( !trst_n_pad_in )    tdo_pad_oe   <= 1'b0;
        else                     tdo_pad_oe   <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) );
 
 
 
 
 
 
 
 
 
 
 
 
`ifndef SYNTHESIS
 
reg [8*16-1:0] tap_string;
 
always @(tap_state) begin
   case (tap_state)
      TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";
      RUN_TEST_IDLE:    tap_string = "RUN_TEST_IDLE";
      SELECT_DR_SCAN:   tap_string = "SELECT_DR_SCAN";
      CAPTURE_DR:       tap_string = "CAPTURE_DR";
      SHIFT_DR:         tap_string = "SHIFT_DR";
      EXIT1_DR:         tap_string = "EXIT1_DR";
      PAUSE_DR:         tap_string = "PAUSE_DR";
      EXIT2_DR:         tap_string = "EXIT2_DR";
      UPDATE_DR:        tap_string = "UPDATE_DR";
      SELECT_IR_SCAN:   tap_string = "SELECT_IR_SCAN";
      CAPTURE_IR:       tap_string = "CAPTURE_IR";
      SHIFT_IR:         tap_string = "SHIFT_IR";
      EXIT1_IR:         tap_string = "EXIT1_IR";
      PAUSE_IR:         tap_string = "PAUSE_IR";
      EXIT2_IR:         tap_string = "EXIT2_IR";
      UPDATE_IR:        tap_string = "UPDATE_IR";
      default:          tap_string = "-XXXXXX-";
   endcase
 
   $display("%t  %m   Tap State   = %s",$realtime, tap_string);
end
 
 
 
 
reg [8*16-1:0] inst_string;
 
always @(instruction) begin
   case (instruction)
      EXTEST: inst_string = "EXTEST";
      SAMPLE: inst_string = "SAMPLE";
      HIGHZ_MODE: inst_string = "HIGHZ_MODE";
      CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";
      CLAMP: inst_string = "CLAMP";
      RPC_DATA: inst_string = "RPC_DATA";
      RPC_ADD: inst_string = "RPC_ADD";
      BYPASS: inst_string = "BYPASS";
      default:          inst_string = "-XXXXXX-";
   endcase
 
   $display("%t  %m   Instruction = %s",$realtime, inst_string);
end
 
`endif
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [tap_sm] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
3
4			`//********************************************************************`
5			`//***`
6			`//********************************************************************`
7
8			`reg [ 3 : 0] next_tap_state;`
9			`reg [ 3 : 0] tap_state;`
10			`reg bypass_tdo;`
11			`reg capture_ir;`
12			`reg next_tdo;`
13			`reg shift_ir;`
14			`reg update_ir;`
15
16
17
18
19
20
21
22
23
24			`assign jtag_reset = ! trst_n_pad_in;`
25
26			`//********************************************************************`
27			`//*** TAP Controller State Machine`
28			`//********************************************************************`
29
30
31			`// TAP state parameters`
32			`localparam TEST_LOGIC_RESET = 4'b1111,`
33			`RUN_TEST_IDLE = 4'b1100,`
34			`SELECT_DR_SCAN = 4'b0111,`
35			`CAPTURE_DR = 4'b0110,`
36			`SHIFT_DR = 4'b0010,`
37			`EXIT1_DR = 4'b0001,`
38			`PAUSE_DR = 4'b0011,`
39			`EXIT2_DR = 4'b0000,`
40			`UPDATE_DR = 4'b0101,`
41			`SELECT_IR_SCAN = 4'b0100,`
42			`CAPTURE_IR = 4'b1110,`
43			`SHIFT_IR = 4'b1010,`
44			`EXIT1_IR = 4'b1001,`
45			`PAUSE_IR = 4'b1011,`
46			`EXIT2_IR = 4'b1000,`
47			`UPDATE_IR = 4'b1101;`
48
49
50
51			`// next state decode for tap controller`
52			`always @(*)`
53			`case (tap_state) // synopsys parallel_case`
54			`TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;`
55			`RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;`
56			`SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR;`
57			`CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;`
58			`SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;`
59			`EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR;`
60			`PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR;`
61			`EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR;`
62			`UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;`
63			`SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;`
64			`CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;`
65			`SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;`
66			`EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR;`
67			`PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR;`
68			`EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR;`
69			`UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;`
70			`endcase`
71
72
73			`//********************************************************************`
74			`//*** TAP Controller State Machine Register`
75			`//********************************************************************`
76
77
78			`always @(posedge clk or negedge trst_n_pad_in)`
79			`if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET;`
80			`else tap_state <= next_tap_state;`
81
82
83
84			`always @(*)`
85			`begin`
86			`shift_ir = (tap_state == SHIFT_IR);`
87			`shift_dr_o = (tap_state == SHIFT_DR);`
88			`update_ir = (tap_state == UPDATE_IR);`
89			`update_dr_o = (tap_state == UPDATE_DR);`
90			`capture_dr_o = (tap_state == CAPTURE_DR);`
91			`capture_ir = (tap_state == CAPTURE_IR);`
92			`end`
93
94
95
96
97			`//******************************************************`
98			`//*** Instruction Register`
99			`//******************************************************`
100
101			`reg [INST_LENGTH-1:0] instruction_buffer;`
102
103
104			`// buffer the instruction register while shifting`
105
106			`always @(posedge clk or negedge trst_n_pad_in)`
107			`if (!trst_n_pad_in) instruction_buffer <= INST_RESET;`
108			`else`
109			`if (capture_ir) instruction_buffer <= INST_RETURN;`
110			`else`
111			`if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};`
112
113			`always @(posedge clk or negedge trst_n_pad_in)`
114			`if (!trst_n_pad_in) instruction <= INST_RESET;`
115			`else`
116			`if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET;`
117			`else`
118			`if (update_ir) instruction <= instruction_buffer;`
119
120
121
122			`//**********************************************************`
123			`// Decode tap_state to get test_logic_reset signal`
124			`//**********************************************************`
125
126
127
128
129			`always @(posedge clk or negedge trst_n_pad_in)`
130			`if (!trst_n_pad_in) test_logic_reset_o <= 1'b1;`
131			`else`
132			`if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1;`
133			`else test_logic_reset_o <= 1'b0;`
134
135
136
137
138			`//**********************************************************`
139			`//** Boundary scan control signals`
140			`//**********************************************************`
141
142
143
144			`always @(posedge clk or negedge trst_n_pad_in)`
145			`if (!trst_n_pad_in) bsr_output_mode <= 1'b0;`
146			`else`
147			`if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0;`
148			`else`
149			`if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST) \|\| (instruction_buffer == CLAMP);`
150
151
152
153			`//**********************************************************`
154			`//** Control chip pads when we are in highz_mode`
155			`//**********************************************************`
156
157
158
159			`always @(posedge clk or negedge trst_n_pad_in)`
160			`if (!trst_n_pad_in) tap_highz_mode <= 1'b0;`
161			`else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0;`
162			`else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE);`
163
164
165
166
167
168
169			`//**********************************************************`
170			`//*** Bypass register`
171			`//**********************************************************`
172
173			`always @(posedge clk or negedge trst_n_pad_in)`
174			`if (!trst_n_pad_in) bypass_tdo <= 1'b0;`
175			`else`
176			`if (capture_dr_o) bypass_tdo <= 1'b0;`
177			`else`
178			`if (shift_dr_o) bypass_tdo <= tdi_pad_in;`
179			`else bypass_tdo <= bypass_tdo;`
180
181
182			`//****************************************************************`
183			`//*** Choose what goes out on the TDO pin`
184			`//****************************************************************`
185			`// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode`
186
187			`wire bypass_select;`
188
189			`assign bypass_select = ( instruction == CLAMP ) \|\| ( instruction == BYPASS );`
190
191
192			`// output the instruction register when tap_state[3] is 1, else`
193			`// put out the appropriate data register.`
194
195
196
197
198			`always@(*)`
199			`begin`
200			`if( tap_state[3] ) next_tdo = instruction_buffer[0];`
201			`else`
202			`if(bypass_select) next_tdo = bypass_tdo;`
203			`else next_tdo = tdo_in;`
204			`end`
205
206			`wire clk_n;`
207			`assign clk_n = ! clk;`
208
209
210			`always @(posedge clk_n or negedge trst_n_pad_in)`
211			`if (!trst_n_pad_in) tdo_pad_out <= 1'b0;`
212			`else tdo_pad_out <= next_tdo;`
213
214
215
216			`// output enable for TDO pad`
217
218			`always @(posedge clk_n or negedge trst_n_pad_in)`
219			`if ( !trst_n_pad_in ) tdo_pad_oe <= 1'b0;`
220			`else tdo_pad_oe <= ( (tap_state == SHIFT_DR) \|\| (tap_state == SHIFT_IR) );`
221
222
223
224
225
226
227
228
229
230
231
232
233			`ifndef SYNTHESIS
234
235			`reg [8*16-1:0] tap_string;`
236
237			`always @(tap_state) begin`
238			`case (tap_state)`
239			`TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";`
240			`RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE";`
241			`SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN";`
242			`CAPTURE_DR: tap_string = "CAPTURE_DR";`
243			`SHIFT_DR: tap_string = "SHIFT_DR";`
244			`EXIT1_DR: tap_string = "EXIT1_DR";`
245			`PAUSE_DR: tap_string = "PAUSE_DR";`
246			`EXIT2_DR: tap_string = "EXIT2_DR";`
247			`UPDATE_DR: tap_string = "UPDATE_DR";`
248			`SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN";`
249			`CAPTURE_IR: tap_string = "CAPTURE_IR";`
250			`SHIFT_IR: tap_string = "SHIFT_IR";`
251			`EXIT1_IR: tap_string = "EXIT1_IR";`
252			`PAUSE_IR: tap_string = "PAUSE_IR";`
253			`EXIT2_IR: tap_string = "EXIT2_IR";`
254			`UPDATE_IR: tap_string = "UPDATE_IR";`
255			`default: tap_string = "-XXXXXX-";`
256			`endcase`
257
258			`$display("%t %m Tap State = %s",$realtime, tap_string);`
259			`end`
260
261
262
263
264			`reg [8*16-1:0] inst_string;`
265
266			`always @(instruction) begin`
267			`case (instruction)`
268			`EXTEST: inst_string = "EXTEST";`
269			`SAMPLE: inst_string = "SAMPLE";`
270			`HIGHZ_MODE: inst_string = "HIGHZ_MODE";`
271			`CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";`
272			`CLAMP: inst_string = "CLAMP";`
273			`RPC_DATA: inst_string = "RPC_DATA";`
274			`RPC_ADD: inst_string = "RPC_ADD";`
275			`BYPASS: inst_string = "BYPASS";`
276			`default: inst_string = "-XXXXXX-";`
277			`endcase`
278
279			`$display("%t %m Instruction = %s",$realtime, inst_string);`
280			`end`
281
282			`endif
283