Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

cde

jtag

classic_rpc_in_reg

 jtag

        test_logic_reset

        test_logic_reset

        capture_dr

        capture_dr

        shift_dr

        shift_dr

        update_dr_clk

        update_dr_clk

        tdi

        tdi

        tdo

        tdo

        select

        select

        shiftcapture_dr_clk

        shiftcapture_dr_clk

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      jtag_classic_rpc_in_reg

                                verilog

                                verilog

                                cde_jtag_classic_rpc_in_reg

                                                BITS

                                                16

                                                RESET_VALUE

                                                16'h0000

                                        fs-sim

                                rtl

                                verilog:Kactus2:

                                verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

BITS16

RESET_VALUE'h0

capture_value

wire

in

BITS-10

test_logic_reset

wire

in

capture_dr

wire

in

shift_dr

wire

in

update_dr_clk

wire

in

tdi

wire

in

tdo

wire

out

select

wire

in

shiftcapture_dr_clk

wire

in

      fs-common

        ../verilog/classic_rpc_in_reg

        verilogSourcefragment

        ../verilog/copyright

        verilogSourceinclude

      fs-sim

        ../verilog/common/jtag_classic_rpc_in_reg

        verilogSourcemodule

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/common/jtag_classic_rpc_in_reg

        verilogSourcemodule

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir

      fs-lint

        dest_dir../views/syn/

        verilogSourcelibraryDir