URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_reg.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
rpc_reg
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_rpc_reg
    
  

 
 
 
 

 
 
 
 
 

 
 
 
 
                
                        
                                verilog
                                verilog
                                cde_jtag_rpc_reg
                                
                                        
                                                BITS
                                                16
                                        
                                        
                                                RESET_VALUE
                                                16'h0000
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
       
 
 
                        
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

BITS16
RESET_VALUE'h0

 

 
clk
wire
in

 
reset
wire
in

 
 
tdi
wire
in

 
select
wire
in

 
update_dr
wire
in

 
capture_dr
wire
in

 
shift_dr
wire
in

 
 
tdo
wire
out

 
 
capture_value
wire
in
BITS-10

 
 
update_value
reg
out
BITS-10

 
 
 
 

 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/jtag_rpc_reg
        verilogSourcefragment
      
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_rpc_reg
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_rpc_reg
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_reg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`rpc_reg`
16	131	jt_eaton
17
18	135	jt_eaton
19	131	jt_eaton
20
21
22
23
24
25	135	jt_eaton
26			`gen_verilog`
27			`104.0`
28			`none`
29			`:common:`
30			`tools/verilog/gen_verilog`
31
32
33			`destination`
34			`jtag_rpc_reg`
35
36
37
38	131	jt_eaton
39
40
41
42	135	jt_eaton
43	131	jt_eaton
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50
51
52
53	135	jt_eaton
54
55			`verilog`
56			`verilog`
57			`cde_jtag_rpc_reg`
58
59
60			`BITS`
61			`16`
62
63
64			`RESET_VALUE`
65			`16'h0000`
66
67
68
69			`fs-sim`
70
71
72
73	131	jt_eaton
74
75
76	135	jt_eaton
77
78	131	jt_eaton
79
80	135	jt_eaton
81			`rtl`
82			`verilog:Kactus2:`
83			`verilog`
84
85	131	jt_eaton
86
87	135	jt_eaton
88			`verilog`
89
90
91			`ipxact:library="Testbench"`
92			`ipxact:name="toolflow"`
93			`ipxact:version="verilog"/>`
94
95
96	131	jt_eaton
97
98
99	135	jt_eaton
100			`common:common:`
101			`Verilog`
102
103
104			`fs-common`
105
106
107	131	jt_eaton
108
109
110
111
112	135	jt_eaton
113			`sim:Simulation:`
114			`Verilog`
115
116
117			`fs-sim`
118
119
120	131	jt_eaton
121	135	jt_eaton
122			`syn:Synthesis:`
123			`Verilog`
124
125
126			`fs-syn`
127
128
129	131	jt_eaton
130
131
132	135	jt_eaton
133			`doc`
134
135
136			`ipxact:library="Testbench"`
137			`ipxact:name="toolflow"`
138			`ipxact:version="documentation"/>`
139
140			`:Documentation:`
141			`Verilog`
142
143	131	jt_eaton
144
145
146
147
148
149	135	jt_eaton
150	131	jt_eaton
151
152
153	135	jt_eaton
154			`BITS16`
155			`RESET_VALUE'h0`
156
157	131	jt_eaton
158	135	jt_eaton
159	131	jt_eaton
160	135	jt_eaton	`clk`
161			`wire`
162			`in`
163
164	131	jt_eaton
165	135	jt_eaton	`reset`
166			`wire`
167			`in`
168
169	131	jt_eaton
170
171	135	jt_eaton	`tdi`
172			`wire`
173			`in`
174
175	131	jt_eaton
176	135	jt_eaton	`select`
177			`wire`
178			`in`
179
180	131	jt_eaton
181	135	jt_eaton	`update_dr`
182			`wire`
183			`in`
184
185	131	jt_eaton
186	135	jt_eaton	`capture_dr`
187			`wire`
188			`in`
189
190	131	jt_eaton
191	135	jt_eaton	`shift_dr`
192			`wire`
193			`in`
194
195	131	jt_eaton
196
197	135	jt_eaton	`tdo`
198			`wire`
199			`out`
200
201	131	jt_eaton
202
203	135	jt_eaton	`capture_value`
204			`wire`
205			`in`
206			`BITS-10`
207
208	131	jt_eaton
209
210	135	jt_eaton	`update_value`
211			`reg`
212			`out`
213			`BITS-10`
214
215	131	jt_eaton
216
217
218
219	135	jt_eaton
220	131	jt_eaton
221	135	jt_eaton
222	131	jt_eaton
223
224
225	135	jt_eaton
226
227
228
229
230			`fs-common`
231
232
233
234			`../verilog/jtag_rpc_reg`
235			`verilogSourcefragment`
236
237
238
239
240
241			`fs-sim`
242
243	134	jt_eaton
244	135	jt_eaton
245
246			`../verilog/copyright`
247			`verilogSourceinclude`
248
249	134	jt_eaton
250
251	135	jt_eaton
252
253			`../verilog/common/jtag_rpc_reg`
254			`verilogSourcemodule`
255
256	134	jt_eaton
257
258
259	135	jt_eaton
260			`dest_dir`
261			`../views/syn/`
262			`verilogSourcelibraryDir`
263
264	134	jt_eaton
265	135	jt_eaton
266	134	jt_eaton
267
268	135	jt_eaton
269			`fs-syn`
270	134	jt_eaton
271	135	jt_eaton
272
273			`../verilog/copyright`
274			`verilogSourceinclude`
275
276	134	jt_eaton
277
278	135	jt_eaton
279
280			`../verilog/common/jtag_rpc_reg`
281			`verilogSourcemodule`
282
283	134	jt_eaton
284
285	135	jt_eaton
286			`dest_dir`
287			`../views/syn/`
288			`verilogSourcelibraryDir`
289
290	134	jt_eaton
291
292
293	135	jt_eaton
294	134	jt_eaton
295
296	135	jt_eaton
297	134	jt_eaton
298	135	jt_eaton	`fs-lint`
299
300			`dest_dir../views/syn/`
301			`verilogSourcelibraryDir`
302
303	134	jt_eaton
304	135	jt_eaton
305	134	jt_eaton
306
307
308
309	135	jt_eaton
310	134	jt_eaton
311
312
313
314
315
316
317
318
319	135	jt_eaton