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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_classic_sync_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
classic_sync_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_sync_tb
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_SEL8
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12
    JTAG_USER2_WIDTH24
    JTAG_USER2_RESET24'h123456
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
 
        
        
        Bfm
        
        
        
 
 
 
       
 
              
              Params
              
              
                                   ipxact:library="cde"
                                   ipxact:name="jtag"
                                   ipxact:version="tap_dut.params"/>
             
              
 
 
              
                Bfm
                Bfm              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
 
 
 
 
      
        
        ../verilog/tb.rpc_2
        verilogSource
        fragment
      
 
 
   
 
 
   
      fs-sim
 
 
 
 
 
      
        
        ../verilog/common/jtag_classic_sync_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/jtag_classic_sync_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`classic_sync_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`jtag_classic_sync_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50			`JTAG_SEL8`
51			`JTAG_USER1_WIDTH8`
52			`JTAG_USER1_RESET8'h12`
53			`JTAG_USER2_WIDTH24`
54			`JTAG_USER2_RESET24'h123456`
55			`JTAG_MODEL_DIVCNT 4'h4`
56			`JTAG_MODEL_SIZE 4`
57
58	131	jt_eaton
59
60	135	jt_eaton
61
62			`Bfm`
63
64
65
66	131	jt_eaton
67
68
69	135	jt_eaton
70	131	jt_eaton
71	135	jt_eaton
72			`Params`
73
74
75			`ipxact:library="cde"`
76			`ipxact:name="jtag"`
77			`ipxact:version="tap_dut.params"/>`
78
79
80	131	jt_eaton
81
82	135	jt_eaton
83			`Bfm`
84			`Bfm`
85	131	jt_eaton
86
87	135	jt_eaton
88			`icarus`
89
90
91			`ipxact:library="Testbench"`
92			`ipxact:name="toolflow"`
93			`ipxact:version="icarus"/>`
94
95
96	131	jt_eaton
97
98
99
100	135	jt_eaton
101			`common:common:`
102			`Verilog`
103
104
105			`fs-common`
106
107
108	131	jt_eaton
109
110	135	jt_eaton
111			`sim:Simulation:`
112			`Verilog`
113
114
115			`fs-sim`
116
117
118	131	jt_eaton
119	135	jt_eaton
120			`lint:Lint:`
121			`Verilog`
122
123
124			`fs-lint`
125
126
127	131	jt_eaton
128	135	jt_eaton
129	131	jt_eaton
130
131
132
133	135	jt_eaton
134	131	jt_eaton
135
136
137
138
139	135	jt_eaton
140	131	jt_eaton
141
142	135	jt_eaton
143			`fs-common`
144	131	jt_eaton
145
146
147
148
149	135	jt_eaton
150
151			`../verilog/tb.rpc_2`
152			`verilogSource`
153			`fragment`
154
155	131	jt_eaton
156
157	135	jt_eaton
158	131	jt_eaton
159
160	135	jt_eaton
161			`fs-sim`
162	131	jt_eaton
163
164
165
166
167	135	jt_eaton
168
169			`../verilog/common/jtag_classic_sync_tb`
170			`verilogSourcemodule`
171
172	131	jt_eaton
173
174	135	jt_eaton
175	131	jt_eaton
176
177	135	jt_eaton
178			`fs-lint`
179
180
181			`../verilog/common/jtag_classic_sync_tb`
182			`verilogSourcemodule`
183
184	131	jt_eaton
185
186	135	jt_eaton
187	131	jt_eaton
188
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194	135	jt_eaton
195
196
197
198

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_classic_sync_tb.xml] - Blame information for rev 135