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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [jtag_classic_rpc_in_reg_dutg.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
cde
jtag
classic_rpc_in_reg_dutg.design

 

capture_dr



 

capture_value



 

select



 

shift_dr



 

shiftcapture_dr_clk



 

tdi



 

tdo



 

test_logic_reset



 
 


 

dut


 BITS
 RESET_VALUE





Line No.	Rev	Author	Line
1	131	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`cde`
17			`jtag`
18			`classic_rpc_in_reg_dutg.design`
19
20	131	jt_eaton
21	135	jt_eaton
22			`capture_dr`
23
24
25
26	131	jt_eaton
27	135	jt_eaton
28			`capture_value`
29
30
31
32	131	jt_eaton
33	135	jt_eaton
34			`select`
35
36
37
38	131	jt_eaton
39	135	jt_eaton
40			`shift_dr`
41
42
43
44	131	jt_eaton
45	135	jt_eaton
46			`shiftcapture_dr_clk`
47
48
49
50	131	jt_eaton
51	135	jt_eaton
52			`tdi`
53
54
55
56	131	jt_eaton
57	135	jt_eaton
58			`tdo`
59
60
61
62	131	jt_eaton
63	135	jt_eaton
64			`test_logic_reset`
65
66
67
68	131	jt_eaton
69
70	135	jt_eaton
71
72	131	jt_eaton
73	135	jt_eaton
74			`dut`
75
76
77			`BITS`
78			`RESET_VALUE`
79
80
81
82

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [jtag_classic_rpc_in_reg_dutg.design.xml] - Blame information for rev 135