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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_serial_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
mult
serial_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      mult_serial_tb
    
  

 
 
 

 
 
 
 
 
 
 
 

       
 
              
              Params
              
              
                                   ipxact:library="cde"
                                   ipxact:name="mult"
                                   ipxact:version="serial_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="cde"
                                   ipxact:name="mult"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
   
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/mult_serial_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/mult_serial_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 

 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`mult`
15			`serial_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`mult_serial_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48
49	135	jt_eaton
50
51	131	jt_eaton
52	135	jt_eaton
53			`Params`
54
55
56			`ipxact:library="cde"`
57			`ipxact:name="mult"`
58			`ipxact:version="serial_dut.params"/>`
59
60
61	131	jt_eaton
62
63	135	jt_eaton
64			`Bfm`
65
66			`ipxact:library="cde"`
67			`ipxact:name="mult"`
68			`ipxact:version="bfm.design"/>`
69
70	131	jt_eaton
71
72
73	135	jt_eaton
74			`icarus`
75
76
77			`ipxact:library="Testbench"`
78			`ipxact:name="toolflow"`
79			`ipxact:version="icarus"/>`
80
81
82	131	jt_eaton
83
84
85
86	135	jt_eaton
87			`common:common:`
88			`Verilog`
89
90
91			`fs-common`
92
93
94	131	jt_eaton
95	135	jt_eaton
96			`sim:Simulation:`
97			`Verilog`
98
99
100			`fs-sim`
101
102
103	131	jt_eaton
104
105	135	jt_eaton
106			`lint:Lint:`
107			`Verilog`
108
109
110			`fs-lint`
111
112
113	131	jt_eaton
114	135	jt_eaton
115	131	jt_eaton
116
117
118
119	135	jt_eaton
120	131	jt_eaton
121
122
123
124	135	jt_eaton
125	131	jt_eaton
126	135	jt_eaton
127			`fs-common`
128	131	jt_eaton
129	135	jt_eaton
130
131			`../verilog/top`
132			`verilogSourcefragment`
133
134	131	jt_eaton
135	135	jt_eaton
136	131	jt_eaton
137	135	jt_eaton
138			`fs-sim`
139	131	jt_eaton
140
141
142	135	jt_eaton
143
144			`../verilog/common/mult_serial_tb`
145			`verilogSourcemodule`
146
147	131	jt_eaton
148
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155	135	jt_eaton
156			`fs-lint`
157	131	jt_eaton
158	135	jt_eaton
159
160			`../verilog/synthesys`
161			`verilogSourceinclude`
162
163	131	jt_eaton
164
165	135	jt_eaton
166
167			`../verilog/common/mult_serial_tb`
168			`verilogSourcemodule`
169
170	131	jt_eaton
171
172
173
174	135	jt_eaton
175	131	jt_eaton
176
177
178
179	135	jt_eaton
180	131	jt_eaton
181
182
183
184
185
186	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_serial_tb.xml] - Blame information for rev 135