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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
in_dig
 
 
 
 

 
 pad_ring
 
 
  
      
  
          
            
        PAD_in
        PAD        
            
          
        
      
  
 
 
 
 
 
 pad
  
 
  
      
  
          
            
        pad_in
        pad_in        
            
          
        
      
  
 
 
 
 
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_in_dig
    
  

 
 
 
 

 
 
 

 
 
 
                
                        
                                verilog
                                verilog
                                cde_pad_in_dig
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
  
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 

WIDTH1

 
 
 

 
PAD
wire
in
WIDTH-10

 
pad_in
wire
out
WIDTH-10

 
 
 
 
 
 
 
 

 

 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_in_dig
        verilogSourcefragment
      
 
   
 
 
 
   
      fs-sim
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_dig
        verilogSourcemodule
      
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 

 
 

 
 
 
 
 
 
 
 

refdes
P?
600
700
5
10
1
1
2

 

module_name
cde_pad_in_dig
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
pad
0
-400
0
10
0
0
0

 
 
 

version
in_dig
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_pad_in_dig
 
 

 geda-project.org
 symbols
 pads
 def
 in_pad
 200
 200

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 400
 PAD
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 400
 pad_in
 0

 
 

 
 
 

vector
 
 

 geda-project.org
 symbols
 pads
 def
 in_pad
 200
 200

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 400
 PAD
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 400
 pad_in
 0

 
 

 
 
 
 
 

 
 


 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2	131	jt_eaton
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`pad`
15			`in_dig`
16	131	jt_eaton
17
18
19
20	135	jt_eaton
21	131	jt_eaton
22	135	jt_eaton	`pad_ring`
23
24	131	jt_eaton
25	135	jt_eaton
26
27
28
29
30			`PAD_in`
31			`PAD`
32
33
34
35
36
37	131	jt_eaton
38	135	jt_eaton
39	131	jt_eaton
40
41
42	135	jt_eaton	`pad`
43
44	131	jt_eaton
45	135	jt_eaton
46
47
48
49
50			`pad_in`
51			`pad_in`
52
53
54
55
56
57
58	131	jt_eaton
59
60
61
62
63	135	jt_eaton
64	131	jt_eaton
65
66	135	jt_eaton
67	131	jt_eaton
68
69	134	jt_eaton
70
71	135	jt_eaton
72			`gen_verilog`
73			`104.0`
74			`none`
75			`:common:`
76			`tools/verilog/gen_verilog`
77
78
79			`destination`
80			`pad_in_dig`
81
82
83
84	134	jt_eaton
85
86
87
88	135	jt_eaton
89	134	jt_eaton
90
91	131	jt_eaton
92	135	jt_eaton
93	131	jt_eaton
94
95	134	jt_eaton
96	135	jt_eaton
97
98			`verilog`
99			`verilog`
100			`cde_pad_in_dig`
101
102
103			`WIDTH`
104			`1`
105
106
107
108			`fs-sim`
109
110
111
112	134	jt_eaton
113
114	135	jt_eaton
115	134	jt_eaton
116	135	jt_eaton
117			`rtl`
118			`verilog:Kactus2:`
119			`verilog`
120
121	131	jt_eaton
122	135	jt_eaton
123			`verilog`
124
125
126			`ipxact:library="Testbench"`
127			`ipxact:name="toolflow"`
128			`ipxact:version="verilog"/>`
129
130
131	131	jt_eaton
132
133
134	135	jt_eaton
135			`common:common:`
136			`Verilog`
137
138
139			`fs-common`
140
141
142	131	jt_eaton
143
144	135	jt_eaton
145			`sim:Simulation:`
146			`Verilog`
147
148
149			`fs-sim`
150
151
152	131	jt_eaton
153	135	jt_eaton
154			`syn:Synthesis:`
155			`Verilog`
156
157
158			`fs-syn`
159
160
161	131	jt_eaton
162	135	jt_eaton
163			`doc`
164
165
166			`ipxact:library="Testbench"`
167			`ipxact:name="toolflow"`
168			`ipxact:version="documentation"/>`
169
170			`:Documentation:`
171			`Verilog`
172
173	131	jt_eaton
174
175	135	jt_eaton
176	131	jt_eaton
177	135	jt_eaton
178			`WIDTH1`
179
180	131	jt_eaton
181
182
183	135	jt_eaton
184	131	jt_eaton
185	135	jt_eaton	`PAD`
186			`wire`
187			`in`
188			`WIDTH-10`
189
190	131	jt_eaton
191	135	jt_eaton	`pad_in`
192			`wire`
193			`out`
194			`WIDTH-10`
195
196	131	jt_eaton
197
198
199
200
201
202
203
204	135	jt_eaton
205	131	jt_eaton
206	135	jt_eaton
207	134	jt_eaton
208
209
210
211
212	135	jt_eaton
213	134	jt_eaton
214
215	131	jt_eaton
216	135	jt_eaton
217			`fs-common`
218	134	jt_eaton
219	135	jt_eaton
220
221			`../verilog/pad_in_dig`
222			`verilogSourcefragment`
223
224	134	jt_eaton
225	135	jt_eaton
226	134	jt_eaton
227
228
229	135	jt_eaton
230			`fs-sim`
231	134	jt_eaton
232	131	jt_eaton
233	135	jt_eaton
234
235			`../verilog/copyright`
236			`verilogSourceinclude`
237
238	131	jt_eaton
239
240	135	jt_eaton
241
242			`../verilog/common/pad_in_dig`
243			`verilogSourcemodule`
244
245	134	jt_eaton
246
247
248	135	jt_eaton
249			`dest_dir`
250			`../views/sim/`
251			`verilogSourcelibraryDir`
252
253	134	jt_eaton
254	135	jt_eaton
255	134	jt_eaton
256
257	135	jt_eaton
258			`fs-syn`
259	131	jt_eaton
260
261	135	jt_eaton
262
263			`../verilog/copyright`
264			`verilogSourceinclude`
265
266	131	jt_eaton
267
268	135	jt_eaton
269
270			`../verilog/common/pad_in_dig`
271			`verilogSourcemodule`
272
273	131	jt_eaton
274
275	135	jt_eaton
276			`dest_dir`
277			`../views/syn/`
278			`verilogSourcelibraryDir`
279
280	131	jt_eaton
281
282
283	135	jt_eaton
284	131	jt_eaton
285
286
287	135	jt_eaton
288	131	jt_eaton
289	135	jt_eaton	`fs-lint`
290
291			`dest_dir`
292			`../views/syn/`
293			`verilogSourcelibraryDir`
294
295	131	jt_eaton
296	135	jt_eaton
297	131	jt_eaton
298
299
300
301	135	jt_eaton
302	131	jt_eaton
303
304
305	135	jt_eaton
306
307
308
309
310
311
312
313
314
315
316
317
318
319			`refdes`
320			`P?`
321			`600`
322			`700`
323			`5`
324			`10`
325			`1`
326			`1`
327			`2`
328
329
330
331			`module_name`
332			`cde_pad_in_dig`
333			`400`
334			`0`
335			`5`
336			`10`
337			`0`
338			`1`
339			`2`
340
341
342
343			`vendor`
344			`opencores.org`
345			`0`
346			`-200`
347			`0`
348			`10`
349			`0`
350			`0`
351			`0`
352
353
354
355			`library`
356			`cde`
357			`0`
358			`-300`
359			`0`
360			`10`
361			`0`
362			`0`
363			`0`
364
365
366
367
368			`component`
369			`pad`
370			`0`
371			`-400`
372			`0`
373			`10`
374			`0`
375			`0`
376			`0`
377
378
379
380
381
382			`version`
383			`in_dig`
384			`0`
385			`-500`
386			`0`
387			`10`
388			`0`
389			`0`
390			`0`
391
392
393
394
395
396
397
398
399
400
401
402
403			`cde_pad_in_dig`
404
405
406
407			`geda-project.org`
408			`symbols`
409			`pads`
410			`def`
411			`in_pad`
412			`200`
413			`200`
414
415
416
417
418			`geda-project.org`
419			`symbols`
420			`pins`
421			`def`
422			`in_wire`
423			`0`
424			`400`
425			`PAD`
426			`0`
427
428
429
430
431
432
433			`geda-project.org`
434			`symbols`
435			`pins`
436			`def`
437			`out_wire`
438			`1300`
439			`400`
440			`pad_in`
441			`0`
442
443
444
445
446
447
448
449
450			`vector`
451
452
453
454			`geda-project.org`
455			`symbols`
456			`pads`
457			`def`
458			`in_pad`
459			`200`
460			`200`
461
462
463
464
465
466
467			`geda-project.org`
468			`symbols`
469			`pins`
470			`def`
471			`in_bus`
472			`0`
473			`400`
474			`PAD`
475			`0`
476
477
478
479
480
481
482			`geda-project.org`
483			`symbols`
484			`pins`
485			`def`
486			`out_bus`
487			`1300`
488			`400`
489			`pad_in`
490			`0`
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515