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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_od_dig.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
od_dig
 
 
 
 
 
 

 
 pad_ring
  
 
  
      
  
          
            
        PAD_io
        PAD
 
            
          
        
      
  
 
 
 
 
 
 pad
  
 
  
      
  
    
      
        pad_oe
        pad_oe
      
      
        pad_in
        pad_in
      
    
 
      
      
 
 
 
 
 
 
 
 
 

 
 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_od_dig
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_od_dig
    
  

 
 
 
 

 
 
 
 

       
 
            
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
PAD
wire
inout

 
pad_in
wire
out

 
pad_oe
wire
in

 
 

 

 
 
 
 

 
   
      fs-sim
 
     
        
        ../verilog/pad_od_sim
        verilogSourcefragment
      
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/pad_od_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
     
        
        ../verilog/pad_od_syn
        verilogSourcefragment
      
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/pad_od_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 

 
 
 
 
 

 
 

 
 
 
 
 
 
 
 

refdes
P?
800
1000
5
10
1
1
2

 

module_name
cde_pad_od_dig
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
pad
0
-400
0
10
0
0
0

 
 
 

version
od_dig
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_pad_od_dig
 
 

 geda-project.org
 symbols
 pads
 def
 io_pad
 100
 00

 
 

 geda-project.org
 symbols
 pads
 def
 oe_wire
 0
 600

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 600
 PAD
 0

 
 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 900
 pad_oe
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire_m
 000
 200
 pad_in
 0

 
 
 
 

 
 
 
 
 
 

vector
 
 

 geda-project.org
 symbols
 pads
 def
 io_pad
 100
 00

 
 

 geda-project.org
 symbols
 pads
 def
 oe_bus
 0
 600

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 600
 PAD
 0

 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 900
 pad_oe
 0

 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus_m
 000
 200
 pad_in
 0

 
 
 
 

 
 
 
 
 
 

 
 


 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_od_dig.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`pad`
15			`od_dig`
16	131	jt_eaton
17
18
19
20
21
22	135	jt_eaton
23	131	jt_eaton
24	135	jt_eaton	`pad_ring`
25
26	131	jt_eaton
27	135	jt_eaton
28
29
30
31
32			`PAD_io`
33			`PAD`
34	131	jt_eaton
35	135	jt_eaton
36
37
38
39
40	131	jt_eaton
41	135	jt_eaton
42	131	jt_eaton
43
44
45	135	jt_eaton	`pad`
46
47	131	jt_eaton
48	135	jt_eaton
49
50
51
52
53			`pad_oe`
54			`pad_oe`
55
56
57			`pad_in`
58			`pad_in`
59
60
61	131	jt_eaton
62	135	jt_eaton
63
64	131	jt_eaton
65	135	jt_eaton
66	131	jt_eaton
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72
73	135	jt_eaton
74	131	jt_eaton
75
76	134	jt_eaton
77
78	135	jt_eaton
79	134	jt_eaton
80
81
82
83	135	jt_eaton
84			`gen_verilog_sim`
85			`104.0`
86			`none`
87			`:Simulation:`
88			`tools/verilog/gen_verilog`
89
90
91			`destination`
92			`pad_od_dig`
93
94
95
96	134	jt_eaton
97
98	135	jt_eaton
99			`gen_verilog_syn`
100			`104.0`
101			`none`
102			`:Synthesis:`
103			`tools/verilog/gen_verilog`
104
105
106			`destination`
107			`pad_od_dig`
108
109
110
111	134	jt_eaton
112
113
114	131	jt_eaton
115	135	jt_eaton
116	131	jt_eaton
117
118	134	jt_eaton
119
120	135	jt_eaton
121
122	134	jt_eaton
123	135	jt_eaton
124			`verilog`
125
126
127			`ipxact:library="Testbench"`
128			`ipxact:name="toolflow"`
129			`ipxact:version="verilog"/>`
130
131
132	134	jt_eaton
133	131	jt_eaton
134
135
136
137
138	135	jt_eaton
139			`sim:Simulation:`
140			`Verilog`
141
142
143			`fs-sim`
144
145
146	131	jt_eaton
147	135	jt_eaton
148			`syn:Synthesis:`
149			`Verilog`
150
151
152			`fs-syn`
153
154
155	131	jt_eaton
156
157
158	135	jt_eaton
159			`doc`
160
161
162			`ipxact:library="Testbench"`
163			`ipxact:name="toolflow"`
164			`ipxact:version="documentation"/>`
165
166			`:Documentation:`
167			`Verilog`
168
169	131	jt_eaton
170
171	135	jt_eaton
172	131	jt_eaton
173
174
175
176	135	jt_eaton
177	131	jt_eaton
178	135	jt_eaton	`PAD`
179			`wire`
180			`inout`
181
182	131	jt_eaton
183	135	jt_eaton	`pad_in`
184			`wire`
185			`out`
186
187	131	jt_eaton
188	135	jt_eaton	`pad_oe`
189			`wire`
190			`in`
191
192	131	jt_eaton
193
194	135	jt_eaton
195	131	jt_eaton
196	135	jt_eaton
197	131	jt_eaton
198	134	jt_eaton
199
200
201	135	jt_eaton
202	134	jt_eaton
203	135	jt_eaton
204			`fs-sim`
205	134	jt_eaton
206	135	jt_eaton
207
208			`../verilog/pad_od_sim`
209			`verilogSourcefragment`
210
211	131	jt_eaton
212	135	jt_eaton
213
214			`../verilog/copyright`
215			`verilogSourceinclude`
216
217	131	jt_eaton
218	135	jt_eaton
219
220			`../verilog/sim/pad_od_dig`
221			`verilogSourcemodule`
222
223	131	jt_eaton
224
225	134	jt_eaton
226	135	jt_eaton
227			`dest_dir`
228			`../views/sim/`
229			`verilogSourcelibraryDir`
230
231	134	jt_eaton
232	135	jt_eaton
233	134	jt_eaton
234
235	135	jt_eaton
236			`fs-syn`
237	131	jt_eaton
238	135	jt_eaton
239
240			`../verilog/pad_od_syn`
241			`verilogSourcefragment`
242
243	131	jt_eaton
244	135	jt_eaton
245
246			`../verilog/copyright`
247			`verilogSourceinclude`
248
249	131	jt_eaton
250	135	jt_eaton
251
252			`../verilog/syn/pad_od_dig`
253			`verilogSourcemodule`
254
255	131	jt_eaton
256
257	135	jt_eaton
258			`dest_dir`
259			`../views/syn/`
260			`verilogSourcelibraryDir`
261
262	131	jt_eaton
263
264
265	135	jt_eaton
266	131	jt_eaton
267
268	135	jt_eaton
269	131	jt_eaton
270	135	jt_eaton	`fs-lint`
271
272			`dest_dir`
273			`../views/syn/`
274			`verilogSourcelibraryDir`
275
276	131	jt_eaton
277	135	jt_eaton
278	131	jt_eaton
279
280
281
282
283
284	135	jt_eaton
285	131	jt_eaton
286
287
288	135	jt_eaton
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303			`refdes`
304			`P?`
305			`800`
306			`1000`
307			`5`
308			`10`
309			`1`
310			`1`
311			`2`
312
313
314
315			`module_name`
316			`cde_pad_od_dig`
317			`400`
318			`0`
319			`5`
320			`10`
321			`0`
322			`1`
323			`2`
324
325
326
327			`vendor`
328			`opencores.org`
329			`0`
330			`-200`
331			`0`
332			`10`
333			`0`
334			`0`
335			`0`
336
337
338
339			`library`
340			`cde`
341			`0`
342			`-300`
343			`0`
344			`10`
345			`0`
346			`0`
347			`0`
348
349
350
351
352			`component`
353			`pad`
354			`0`
355			`-400`
356			`0`
357			`10`
358			`0`
359			`0`
360			`0`
361
362
363
364
365
366			`version`
367			`od_dig`
368			`0`
369			`-500`
370			`0`
371			`10`
372			`0`
373			`0`
374			`0`
375
376
377
378
379
380
381
382
383
384
385
386
387			`cde_pad_od_dig`
388
389
390
391			`geda-project.org`
392			`symbols`
393			`pads`
394			`def`
395			`io_pad`
396			`100`
397			`00`
398
399
400
401
402			`geda-project.org`
403			`symbols`
404			`pads`
405			`def`
406			`oe_wire`
407			`0`
408			`600`
409
410
411
412
413
414
415			`geda-project.org`
416			`symbols`
417			`pins`
418			`def`
419			`out_wire`
420			`1300`
421			`600`
422			`PAD`
423			`0`
424
425
426
427
428
429
430
431
432
433
434			`geda-project.org`
435			`symbols`
436			`pins`
437			`def`
438			`in_wire`
439			`0`
440			`900`
441			`pad_oe`
442			`0`
443
444
445
446
447
448
449			`geda-project.org`
450			`symbols`
451			`pins`
452			`def`
453			`out_wire_m`
454			`000`
455			`200`
456			`pad_in`
457			`0`
458
459
460
461
462
463
464
465
466
467
468
469
470
471			`vector`
472
473
474
475			`geda-project.org`
476			`symbols`
477			`pads`
478			`def`
479			`io_pad`
480			`100`
481			`00`
482
483
484
485
486			`geda-project.org`
487			`symbols`
488			`pads`
489			`def`
490			`oe_bus`
491			`0`
492			`600`
493
494
495
496
497
498
499			`geda-project.org`
500			`symbols`
501			`pins`
502			`def`
503			`out_bus`
504			`1300`
505			`600`
506			`PAD`
507			`0`
508
509
510
511
512
513
514
515
516
517			`geda-project.org`
518			`symbols`
519			`pins`
520			`def`
521			`in_bus`
522			`0`
523			`900`
524			`pad_oe`
525			`0`
526
527
528
529
530
531
532
533
534			`geda-project.org`
535			`symbols`
536			`pins`
537			`def`
538			`out_bus_m`
539			`000`
540			`200`
541			`pad_in`
542			`0`
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571