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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_se_dig.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
se_dig
 
 
 

 
 pad_ring
  
 
  
      
  
          
            
        PAD_io
        PAD       
            
          
        
      
  
 
 
 
 
 pad
  
 
  
      
  
          
      
        pad_out
        pad_out
        
      
      
        pad_oe
        pad_oe
      
      
        pad_in
        pad_in         
      
          
        
      
  
 
 

 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_se_dig
    
  

 
 
 
 

 
 
 

 
 
 
 
                
                        
                                verilog
                                verilog
                                cde_pad_se_dig
                                
                                        
                                                WIDTH
                                                1
                                        
                                        
                                                OE_WIDTH
                                                1
                                        
 
 
 
                                
                                
                                        fs-sim
                                
                        
                
 
 
                
 
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
            
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

  WIDTH1
  OE_WIDTH1

 
 

 
PAD
wire

inout
 WIDTH-10
 

 
pad_in
wire

 out
 WIDTH-10


 
pad_out
wire
 in
 WIDTH-10


 
pad_oe
wire

 in
 OE_WIDTH-10


 
 
 
 
 

 

 
 
 
 
 
 
 
 

 
    
      fs-common
 
      
        
        ../verilog/pad_se_dig
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
  
      fs-sim
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_se_dig
        verilogSourcemodule
      
 
 
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_se_dig
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 

 
 

 
 
 
 
 
 
 
 

refdes
P?
800
1000
5
10
1
1
2

 

module_name
cde_pad_se_dig
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
pad
0
-400
0
10
0
0
0

 
 
 

version
se_dig
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_pad_se_dig
 
 

 geda-project.org
 symbols
 pads
 def
 io_pad
 100
 00

 
 

 geda-project.org
 symbols
 pads
 def
 oe_wire
 0
 600

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 600
 PAD
 0

 
 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 900
 pad_oe
 0

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 600
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_wire_m
 000
 200
 pad_in
 0

 
 
 
 

 
 
 
 
 
 

vector
 
 

 geda-project.org
 symbols
 pads
 def
 io_pad
 100
 00

 
 

 geda-project.org
 symbols
 pads
 def
 oe_bus
 0
 600

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 600
 PAD
 0

 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 900
 pad_oe
 0

 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 600
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_bus_m
 000
 200
 pad_in
 0

 
 
 
 

 
 
 
 

scmd
 
 

 geda-project.org
 symbols
 pads
 def
 io_pad
 100
 00

 
 

 geda-project.org
 symbols
 pads
 def
 oe_wire
 0
 600

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 600
 PAD
 0

 
 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 900
 pad_oe
 0

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 600
 pad_out
 0

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus_m
 000
 200
 pad_in
 0

 
 
 
 

 
 
 
 
 
 

 
 


 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_se_dig.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`pad`
15			`se_dig`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton	`pad_ring`
22
23	131	jt_eaton
24	135	jt_eaton
25
26
27
28
29			`PAD_io`
30			`PAD`
31
32
33
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton	`pad`
41
42	131	jt_eaton
43	135	jt_eaton
44
45
46
47
48			`pad_out`
49			`pad_out`
50
51
52
53			`pad_oe`
54			`pad_oe`
55
56
57			`pad_in`
58			`pad_in`
59
60
61
62
63
64
65	131	jt_eaton
66	135	jt_eaton
67	131	jt_eaton
68
69
70	135	jt_eaton
71	131	jt_eaton
72
73	134	jt_eaton
74
75	135	jt_eaton
76			`gen_verilog`
77			`104.0`
78			`none`
79			`:common:`
80			`tools/verilog/gen_verilog`
81
82
83			`destination`
84			`pad_se_dig`
85
86
87
88	134	jt_eaton
89
90
91
92	135	jt_eaton
93	134	jt_eaton
94
95
96	135	jt_eaton
97	131	jt_eaton
98	134	jt_eaton
99
100
101	135	jt_eaton
102
103			`verilog`
104			`verilog`
105			`cde_pad_se_dig`
106
107
108			`WIDTH`
109			`1`
110
111
112			`OE_WIDTH`
113			`1`
114
115	134	jt_eaton
116
117
118	135	jt_eaton
119
120			`fs-sim`
121
122
123
124	131	jt_eaton
125
126	135	jt_eaton
127	131	jt_eaton
128	135	jt_eaton
129
130			`rtl`
131			`verilog:Kactus2:`
132			`verilog`
133
134	131	jt_eaton
135	135	jt_eaton
136			`verilog`
137
138
139			`ipxact:library="Testbench"`
140			`ipxact:name="toolflow"`
141			`ipxact:version="verilog"/>`
142
143
144	131	jt_eaton
145
146
147	135	jt_eaton
148			`common:common:`
149			`Verilog`
150
151
152			`fs-common`
153
154
155	131	jt_eaton
156
157
158	135	jt_eaton
159			`sim:Simulation:`
160			`Verilog`
161
162
163			`fs-sim`
164
165
166	131	jt_eaton
167	135	jt_eaton
168			`syn:Synthesis:`
169			`Verilog`
170
171
172			`fs-syn`
173
174
175	131	jt_eaton
176
177	135	jt_eaton
178			`doc`
179
180
181			`ipxact:library="Testbench"`
182			`ipxact:name="toolflow"`
183			`ipxact:version="documentation"/>`
184
185			`:Documentation:`
186			`Verilog`
187
188	131	jt_eaton
189
190
191	135	jt_eaton
192	131	jt_eaton
193
194	135	jt_eaton
195			`WIDTH1`
196			`OE_WIDTH1`
197
198	131	jt_eaton
199
200	135	jt_eaton
201	131	jt_eaton
202	135	jt_eaton	`PAD`
203			`wire`
204
205			`inout`
206			`WIDTH-10`
207
208
209	131	jt_eaton
210	135	jt_eaton	`pad_in`
211			`wire`
212
213			`out`
214			`WIDTH-10`
215
216
217	131	jt_eaton
218	135	jt_eaton	`pad_out`
219			`wire`
220			`in`
221			`WIDTH-10`
222
223
224	131	jt_eaton
225	135	jt_eaton	`pad_oe`
226			`wire`
227
228			`in`
229			`OE_WIDTH-10`
230
231
232	131	jt_eaton
233
234
235
236
237	135	jt_eaton
238	134	jt_eaton
239	135	jt_eaton
240	134	jt_eaton
241
242
243
244
245
246
247
248	135	jt_eaton
249	134	jt_eaton
250	135	jt_eaton
251			`fs-common`
252	131	jt_eaton
253	135	jt_eaton
254
255			`../verilog/pad_se_dig`
256			`verilogSourcefragment`
257
258	134	jt_eaton
259
260
261
262
263	135	jt_eaton
264	134	jt_eaton
265
266	131	jt_eaton
267
268	135	jt_eaton
269			`fs-sim`
270	131	jt_eaton
271	135	jt_eaton
272
273			`../verilog/copyright`
274			`verilogSourceinclude`
275
276	131	jt_eaton
277	134	jt_eaton
278	135	jt_eaton
279
280			`../verilog/common/pad_se_dig`
281			`verilogSourcemodule`
282
283	134	jt_eaton
284
285
286	131	jt_eaton
287
288	135	jt_eaton
289			`dest_dir`
290			`../views/sim/`
291			`verilogSourcelibraryDir`
292
293	131	jt_eaton
294	135	jt_eaton
295	131	jt_eaton
296
297	135	jt_eaton
298			`fs-syn`
299	131	jt_eaton
300	135	jt_eaton
301
302			`../verilog/copyright`
303			`verilogSourceinclude`
304
305	131	jt_eaton
306
307	135	jt_eaton
308
309			`../verilog/common/pad_se_dig`
310			`verilogSourcemodule`
311
312	131	jt_eaton
313
314	135	jt_eaton
315			`dest_dir`
316			`../views/syn/`
317			`verilogSourcelibraryDir`
318
319	131	jt_eaton
320
321
322	135	jt_eaton
323	131	jt_eaton
324
325	135	jt_eaton
326	131	jt_eaton
327	135	jt_eaton	`fs-lint`
328
329			`dest_dir`
330			`../views/syn/`
331			`verilogSourcelibraryDir`
332
333	131	jt_eaton
334	135	jt_eaton
335	131	jt_eaton
336
337
338
339	135	jt_eaton
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359			`refdes`
360			`P?`
361			`800`
362			`1000`
363			`5`
364			`10`
365			`1`
366			`1`
367			`2`
368
369
370
371			`module_name`
372			`cde_pad_se_dig`
373			`400`
374			`0`
375			`5`
376			`10`
377			`0`
378			`1`
379			`2`
380
381
382
383			`vendor`
384			`opencores.org`
385			`0`
386			`-200`
387			`0`
388			`10`
389			`0`
390			`0`
391			`0`
392
393
394
395			`library`
396			`cde`
397			`0`
398			`-300`
399			`0`
400			`10`
401			`0`
402			`0`
403			`0`
404
405
406
407
408			`component`
409			`pad`
410			`0`
411			`-400`
412			`0`
413			`10`
414			`0`
415			`0`
416			`0`
417
418
419
420
421
422			`version`
423			`se_dig`
424			`0`
425			`-500`
426			`0`
427			`10`
428			`0`
429			`0`
430			`0`
431
432
433
434
435
436
437
438
439
440
441
442
443			`cde_pad_se_dig`
444
445
446
447			`geda-project.org`
448			`symbols`
449			`pads`
450			`def`
451			`io_pad`
452			`100`
453			`00`
454
455
456
457
458			`geda-project.org`
459			`symbols`
460			`pads`
461			`def`
462			`oe_wire`
463			`0`
464			`600`
465
466
467
468
469
470
471			`geda-project.org`
472			`symbols`
473			`pins`
474			`def`
475			`out_wire`
476			`1300`
477			`600`
478			`PAD`
479			`0`
480
481
482
483
484
485
486
487
488
489
490			`geda-project.org`
491			`symbols`
492			`pins`
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494			`in_wire`
495			`0`
496			`900`
497			`pad_oe`
498			`0`
499
500
501
502
503
504			`geda-project.org`
505			`symbols`
506			`pins`
507			`def`
508			`in_wire`
509			`0`
510			`600`
511			`pad_out`
512			`0`
513
514
515
516
517			`geda-project.org`
518			`symbols`
519			`pins`
520			`def`
521			`out_wire_m`
522			`000`
523			`200`
524			`pad_in`
525			`0`
526
527
528
529
530
531
532
533
534
535
536
537
538
539			`vector`
540
541
542
543			`geda-project.org`
544			`symbols`
545			`pads`
546			`def`
547			`io_pad`
548			`100`
549			`00`
550
551
552
553
554			`geda-project.org`
555			`symbols`
556			`pads`
557			`def`
558			`oe_bus`
559			`0`
560			`600`
561
562
563
564
565
566
567			`geda-project.org`
568			`symbols`
569			`pins`
570			`def`
571			`out_bus`
572			`1300`
573			`600`
574			`PAD`
575			`0`
576
577
578
579
580
581
582
583
584
585			`geda-project.org`
586			`symbols`
587			`pins`
588			`def`
589			`in_bus`
590			`0`
591			`900`
592			`pad_oe`
593			`0`
594
595
596
597
598
599
600
601
602			`geda-project.org`
603			`symbols`
604			`pins`
605			`def`
606			`in_bus`
607			`0`
608			`600`
609			`pad_out`
610			`0`
611
612
613
614
615			`geda-project.org`
616			`symbols`
617			`pins`
618			`def`
619			`out_bus_m`
620			`000`
621			`200`
622			`pad_in`
623			`0`
624
625
626
627
628
629
630
631
632
633
634
635			`scmd`
636
637
638
639			`geda-project.org`
640			`symbols`
641			`pads`
642			`def`
643			`io_pad`
644			`100`
645			`00`
646
647
648
649
650			`geda-project.org`
651			`symbols`
652			`pads`
653			`def`
654			`oe_wire`
655			`0`
656			`600`
657
658
659
660
661
662
663			`geda-project.org`
664			`symbols`
665			`pins`
666			`def`
667			`out_bus`
668			`1300`
669			`600`
670			`PAD`
671			`0`
672
673
674
675
676
677
678
679
680
681
682			`geda-project.org`
683			`symbols`
684			`pins`
685			`def`
686			`in_wire`
687			`0`
688			`900`
689			`pad_oe`
690			`0`
691
692
693
694
695
696			`geda-project.org`
697			`symbols`
698			`pins`
699			`def`
700			`in_bus`
701			`0`
702			`600`
703			`pad_out`
704			`0`
705
706
707
708
709
710			`geda-project.org`
711			`symbols`
712			`pins`
713			`def`
714			`out_bus_m`
715			`000`
716			`200`
717			`pad_in`
718			`0`
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746