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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_tri_dig.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
tri_dig
 

 
 pad_ring
  
  
      
       
          
            
        PAD_out
        PAD
            
          
        
      
  
 
 
 
 
 
 pad
  
 
 
  
      
  
    
      
        pad_out
        pad_out
      
      
        pad_oe
        pad_oe
      
 
    
 
        
      
 
  
 
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_tri_dig
    
  

 
 
 
 

 
 
 

       
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
PAD
wire
inout

 
pad_out
wire
in

 
pad_oe
wire
in

 
 
 
 
 

 

 
 

 
 
 
      fs-common
 
      
        
        ../verilog/pad_tri_dig
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
 
 
 
 
   
      fs-sim
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_tri_dig
        verilogSourcemodule
      
 
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_tri_dig
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 

 
 

 
 
 
 
 
 
 
 

refdes
P?
600
700
5
10
1
1
2

 

module_name
cde_pad_tri_dig
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
pad
0
-400
0
10
0
0
0

 
 
 

version
tri_dig
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_pad_tri_dig
 
 

 geda-project.org
 symbols
 pads
 def
 out_pad
 100
 200

 

 geda-project.org
 symbols
 pads
 def
 oe_wire
 0
 400

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 700
 pad_oe
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 400
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 400
 PAD
 0

 
 

 
 
 
 

vector
 
 

 geda-project.org
 symbols
 pads
 def
 out_pad
 100
 200

 

 geda-project.org
 symbols
 pads
 def
 oe_bus
 0
 400

 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 700
 pad_oe
 0

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 400
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 400
 PAD
 0

 
 

 
 
 
 
 

scmd
 
 

 geda-project.org
 symbols
 pads
 def
 out_pad
 100
 200

 

 geda-project.org
 symbols
 pads
 def
 oe_wire
 0
 400

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 700
 pad_oe
 0

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 400
 pad_out
 0

 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 400
 PAD
 0

 
 

 
 
 
 
 
 
 

 
 


 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_tri_dig.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`tri_dig`
16
17
18
19			`pad_ring`
20
21
22
23
24
25
26			`PAD_out`
27			`PAD`
28
29
30
31
32
33
34
35
36
37
38			`pad`
39
40
41
42
43
44
45
46
47			`pad_out`
48			`pad_out`
49
50
51			`pad_oe`
52			`pad_oe`
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73			`gen_verilog`
74			`104.0`
75			`none`
76			`:common:`
77			`tools/verilog/gen_verilog`
78
79
80			`destination`
81			`pad_tri_dig`
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98			`verilog`
99
100
101			`ipxact:library="Testbench"`
102			`ipxact:name="toolflow"`
103			`ipxact:version="verilog"/>`
104
105
106
107
108
109
110			`common:common:`
111			`Verilog`
112
113
114			`fs-common`
115
116
117
118
119
120
121			`sim:Simulation:`
122			`Verilog`
123
124
125			`fs-sim`
126
127
128
129
130			`syn:Synthesis:`
131			`Verilog`
132
133
134			`fs-syn`
135
136
137
138
139
140			`doc`
141
142
143			`ipxact:library="Testbench"`
144			`ipxact:name="toolflow"`
145			`ipxact:version="documentation"/>`
146
147			`:Documentation:`
148			`Verilog`
149
150
151
152
153
154
155
156
157
158
159			`PAD`
160			`wire`
161			`inout`
162
163
164			`pad_out`
165			`wire`
166			`in`
167
168
169			`pad_oe`
170			`wire`
171			`in`
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-common`
188
189
190
191			`../verilog/pad_tri_dig`
192			`verilogSourcefragment`
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209			`fs-sim`
210
211
212
213
214			`../verilog/copyright`
215			`verilogSourceinclude`
216
217
218
219
220
221			`../verilog/common/pad_tri_dig`
222			`verilogSourcemodule`
223
224
225
226
227
228
229			`dest_dir`
230			`../views/sim/`
231			`verilogSourcelibraryDir`
232
233
234
235
236
237
238			`fs-syn`
239
240
241
242			`../verilog/copyright`
243			`verilogSourceinclude`
244
245
246
247
248
249			`../verilog/common/pad_tri_dig`
250			`verilogSourcemodule`
251
252
253
254
255
256			`dest_dir`
257			`../views/syn/`
258			`verilogSourcelibraryDir`
259
260
261
262
263
264
265
266
267
268			`fs-lint`
269
270			`dest_dir`
271			`../views/syn/`
272			`verilogSourcelibraryDir`
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298			`refdes`
299			`P?`
300			`600`
301			`700`
302			`5`
303			`10`
304			`1`
305			`1`
306			`2`
307
308
309
310			`module_name`
311			`cde_pad_tri_dig`
312			`400`
313			`0`
314			`5`
315			`10`
316			`0`
317			`1`
318			`2`
319
320
321
322			`vendor`
323			`opencores.org`
324			`0`
325			`-200`
326			`0`
327			`10`
328			`0`
329			`0`
330			`0`
331
332
333
334			`library`
335			`cde`
336			`0`
337			`-300`
338			`0`
339			`10`
340			`0`
341			`0`
342			`0`
343
344
345
346
347			`component`
348			`pad`
349			`0`
350			`-400`
351			`0`
352			`10`
353			`0`
354			`0`
355			`0`
356
357
358
359
360
361			`version`
362			`tri_dig`
363			`0`
364			`-500`
365			`0`
366			`10`
367			`0`
368			`0`
369			`0`
370
371
372
373
374
375
376
377
378
379
380
381
382			`cde_pad_tri_dig`
383
384
385
386			`geda-project.org`
387			`symbols`
388			`pads`
389			`def`
390			`out_pad`
391			`100`
392			`200`
393
394
395
396			`geda-project.org`
397			`symbols`
398			`pads`
399			`def`
400			`oe_wire`
401			`0`
402			`400`
403
404
405
406
407
408			`geda-project.org`
409			`symbols`
410			`pins`
411			`def`
412			`in_wire`
413			`0`
414			`700`
415			`pad_oe`
416			`0`
417
418
419
420
421
422
423			`geda-project.org`
424			`symbols`
425			`pins`
426			`def`
427			`in_wire`
428			`0`
429			`400`
430			`pad_out`
431			`0`
432
433
434
435
436			`geda-project.org`
437			`symbols`
438			`pins`
439			`def`
440			`out_wire`
441			`1300`
442			`400`
443			`PAD`
444			`0`
445
446
447
448
449
450
451
452
453
454			`vector`
455
456
457
458			`geda-project.org`
459			`symbols`
460			`pads`
461			`def`
462			`out_pad`
463			`100`
464			`200`
465
466
467
468			`geda-project.org`
469			`symbols`
470			`pads`
471			`def`
472			`oe_bus`
473			`0`
474			`400`
475
476
477
478
479			`geda-project.org`
480			`symbols`
481			`pins`
482			`def`
483			`in_bus`
484			`0`
485			`700`
486			`pad_oe`
487			`0`
488
489
490
491
492
493			`geda-project.org`
494			`symbols`
495			`pins`
496			`def`
497			`in_bus`
498			`0`
499			`400`
500			`pad_out`
501			`0`
502
503
504
505
506			`geda-project.org`
507			`symbols`
508			`pins`
509			`def`
510			`out_bus`
511			`1300`
512			`400`
513			`PAD`
514			`0`
515
516
517
518
519
520
521
522
523
524
525			`scmd`
526
527
528
529			`geda-project.org`
530			`symbols`
531			`pads`
532			`def`
533			`out_pad`
534			`100`
535			`200`
536
537
538
539			`geda-project.org`
540			`symbols`
541			`pads`
542			`def`
543			`oe_wire`
544			`0`
545			`400`
546
547
548
549
550			`geda-project.org`
551			`symbols`
552			`pins`
553			`def`
554			`in_wire`
555			`0`
556			`700`
557			`pad_oe`
558			`0`
559
560
561
562
563
564			`geda-project.org`
565			`symbols`
566			`pins`
567			`def`
568			`in_bus`
569			`0`
570			`400`
571			`pad_out`
572			`0`
573
574
575
576
577			`geda-project.org`
578			`symbols`
579			`pins`
580			`def`
581			`out_bus`
582			`1300`
583			`400`
584			`PAD`
585			`0`
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615