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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_asyncdisable.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
reset
asyncdisable
 
 
 
 

 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 

 
 
 
                
                        
                                verilog
                                verilog
                                cde_reset_asyncdisable
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
  
 
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

WIDTH1

 

 
reset_n
wire
in

 
reset
wire
in

 
atg_asyncdisable
wire
in

 
 
 
sync_reset
wire
in
WIDTH-10

 
 
reset_n_out
wire
out
WIDTH-10

 
 
reset_out
wire
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_asyncdisable.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`reset`
15			`asyncdisable`
16	131	jt_eaton
17
18
19
20	135	jt_eaton
21	131	jt_eaton
22
23
24
25
26
27	135	jt_eaton
28	131	jt_eaton
29
30
31
32
33	135	jt_eaton
34	131	jt_eaton
35	135	jt_eaton
36			`fs-sim`
37	131	jt_eaton
38
39	135	jt_eaton
40			`dest_dir`
41			`../verilog/`
42			`verilogSourcelibraryDir`
43
44	131	jt_eaton
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49			`fs-syn`
50	131	jt_eaton
51	135	jt_eaton
52			`dest_dir`
53			`../verilog/`
54			`verilogSourcelibraryDir`
55
56	131	jt_eaton
57
58
59	135	jt_eaton
60	131	jt_eaton
61
62	135	jt_eaton
63	131	jt_eaton
64	135	jt_eaton	`fs-lint`
65
66			`dest_dir`
67			`../verilog/`
68			`verilogSourcelibraryDir`
69
70	131	jt_eaton
71	135	jt_eaton
72	131	jt_eaton
73
74
75
76	135	jt_eaton
77	131	jt_eaton
78
79
80
81
82	135	jt_eaton
83	131	jt_eaton
84
85	135	jt_eaton
86
87
88			`verilog`
89			`verilog`
90			`cde_reset_asyncdisable`
91
92
93			`WIDTH`
94			`1`
95
96
97
98			`fs-sim`
99
100
101
102
103
104
105
106
107
108
109
110			`rtl`
111			`verilog:Kactus2:`
112			`verilog`
113
114
115
116
117			`sim:Simulation:`
118	131	jt_eaton
119	135	jt_eaton	`Verilog`
120
121
122			`fs-sim`
123
124
125	131	jt_eaton
126	135	jt_eaton
127			`syn:Synthesis:`
128	131	jt_eaton
129	135	jt_eaton	`Verilog`
130
131
132			`fs-syn`
133
134
135	131	jt_eaton
136
137
138
139	135	jt_eaton
140			`doc`
141
142
143			`ipxact:library="Testbench"`
144			`ipxact:name="toolflow"`
145			`ipxact:version="documentation"/>`
146
147			`:Documentation:`
148			`Verilog`
149
150	131	jt_eaton
151
152
153
154	135	jt_eaton
155	131	jt_eaton
156
157
158	135	jt_eaton
159			`WIDTH1`
160
161	131	jt_eaton
162	135	jt_eaton
163	131	jt_eaton
164	135	jt_eaton	`reset_n`
165			`wire`
166			`in`
167
168	131	jt_eaton
169	135	jt_eaton	`reset`
170			`wire`
171			`in`
172
173	131	jt_eaton
174	135	jt_eaton	`atg_asyncdisable`
175			`wire`
176			`in`
177
178	131	jt_eaton
179
180
181	135	jt_eaton	`sync_reset`
182			`wire`
183			`in`
184			`WIDTH-10`
185
186	131	jt_eaton
187
188	135	jt_eaton	`reset_n_out`
189			`wire`
190			`out`
191			`WIDTH-10`
192
193	131	jt_eaton
194
195	135	jt_eaton	`reset_out`
196			`wire`
197			`out`
198			`WIDTH-10`
199
200	131	jt_eaton
201
202
203	135	jt_eaton
204	131	jt_eaton
205	135	jt_eaton
206	131	jt_eaton
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217	135	jt_eaton