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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
serial
both_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      serial_both_tb
    
  

 
 
 

 
 
 
 
 
 
 
 
 

 
       
 
              
              Params
              
              
                                   ipxact:library="cde"
                                   ipxact:name="serial"
                                   ipxact:version="both_dut.params"/>
              
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
      
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
 
 
      
        
        ../verilog/both.tb
        verilogSourcefragment
      
 
   
 
 
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/serial_both_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/serial_both_tb
        verilogSourcemodule
      
 
 
 
 
 
   
 
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`serial`
15			`both_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`serial_both_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48
49
50	135	jt_eaton
51	131	jt_eaton
52	135	jt_eaton
53	131	jt_eaton
54	135	jt_eaton
55			`Params`
56
57
58			`ipxact:library="cde"`
59			`ipxact:name="serial"`
60			`ipxact:version="both_dut.params"/>`
61
62
63	131	jt_eaton
64
65
66	135	jt_eaton
67			`icarus`
68
69
70			`ipxact:library="Testbench"`
71			`ipxact:name="toolflow"`
72			`ipxact:version="icarus"/>`
73
74
75	131	jt_eaton
76
77
78
79	135	jt_eaton
80			`common:common:`
81			`Verilog`
82
83
84			`fs-common`
85
86
87	131	jt_eaton
88
89	135	jt_eaton
90			`sim:Simulation:`
91			`Verilog`
92
93
94			`fs-sim`
95
96
97	131	jt_eaton
98
99
100	135	jt_eaton
101			`lint:Lint:`
102			`Verilog`
103
104
105			`fs-lint`
106
107
108	131	jt_eaton
109
110
111
112
113	135	jt_eaton
114	131	jt_eaton
115
116
117
118	135	jt_eaton
119	131	jt_eaton
120
121
122	135	jt_eaton
123	131	jt_eaton
124
125
126	135	jt_eaton
127			`fs-common`
128	131	jt_eaton
129
130
131	135	jt_eaton
132
133			`../verilog/both.tb`
134			`verilogSourcefragment`
135
136	131	jt_eaton
137	135	jt_eaton
138	131	jt_eaton
139
140
141
142
143
144	135	jt_eaton
145			`fs-sim`
146	131	jt_eaton
147
148
149	135	jt_eaton
150
151			`../verilog/common/serial_both_tb`
152			`verilogSourcemodule`
153
154	131	jt_eaton
155
156	135	jt_eaton
157	131	jt_eaton
158
159	135	jt_eaton
160			`fs-lint`
161	131	jt_eaton
162	135	jt_eaton
163
164			`../verilog/common/serial_both_tb`
165			`verilogSourcemodule`
166
167	131	jt_eaton
168
169
170
171
172	135	jt_eaton
173	131	jt_eaton
174
175
176
177
178	135	jt_eaton
179	131	jt_eaton
180
181
182
183	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [cde_serial_both_tb.xml] - Blame information for rev 135