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// Memory Array

reg [WIDTH-1:0] mem [0:WORDS-1];

// If used as Rom then load a memory image at startup

initial

  begin

  $display("SRAM dp  %m.mem");

  $display("  AddrBits=%d DataBits = %d  Words = %d  ",ADDR,WIDTH,WORDS);

  end

// Write function

always@(posedge clk)

        if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0];

  reg   [ADDR-1:0]          l_raddr;

  reg                       l_cycle;

  always@(posedge clk)

      begin

        l_raddr    <= raddr;

        l_cycle    <=  rd &&  cs ;

      end

generate

if( WRITETHRU)

  begin

  // Read function gets new data if also a write cycle

  // latch the read addr for next cycle

  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block

  wire  [WIDTH-1:0] tmp_rdata;

  assign          tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};

  always@(*)          rdata  =      tmp_rdata;

  end

else

  begin

  // Read function gets old data if also a write cycle

  always@(posedge clk)

        if( rd && cs ) rdata             <= mem[{raddr[ADDR-1:0]}];

        else           rdata             <= {WIDTH{1'b1}};

  end

endgenerate