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            Indicates whether bit steering should be used to map this interface onto a bus of different data width.

Values are "on", "off" (defaults to "off").

            'big': means the most significant element of any multi-element  data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian.

            The number of bits in the least addressable unit. The default is byte addressable (8 bits).

            Describes one of the bus interfaces supported by this component.

            A list of bus interfaces supported by this component.

            Type definition for a busInterface in a component

                    The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes.

                    The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes. Bus definition can be found through a reference in this file.

                    Indicates the usage mode of this instance of the bus interface.

                    Indicates whether a connection to this interface is required for proper component functionality.

                    Listing of maps between component ports and bus ports.

                                Maps a component's port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component.

                                            Logical port from abstraction definition

                                                        Bus port name as specified inside the abstraction definition

                                                        Definition of the logical indecies for a vectored port.

                                                                    Defines which logical bit maps to the physical left bit below

                                                                    Defines which logical bit maps to the physical right bit below

                                            Physical port from this component

                                                        Component port name as specified inside the model port section

                    Indicates whether bit steering should be used to map this interface onto a bus of different data width.

Values are "on", "off" (defaults to "off").

                    'big': means the most significant element of any multi-element  data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian.

            Indicates which system interface is being mirrored. Name must match a group name present on one or more ports in the corresonding bus definition.

            Lists all channel connections between mirror interfaces of this component.

                        Defines a set of mirrored interfaces of this component that are connected to one another.

                                    Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment.

            Contains a list of remap state names and associated port values

                        Contains a list of ports and values in remapPort and a list of registers and values that when all evaluate to true which tell the decoder to enter this remap state. The name attribute identifies the name of the state. If a list of remapPorts and/or remapRegisters is not defined then the condition for that state cannot be defined.

                                    List of ports and their values that shall invoke this remap state.

                                                Contains the name and value of a port on the component, the value indicates the logic value which this port must take to effect the remapping. The portMapRef attribute stores the name of the port which takes that value.

                                                                This attribute identifies a signal on the component which affects the component's memory layout 

                                                                Index for a vectored type port. Must be a number between left and right for the port.

            Group of the different modes a busInterface can take on in a component

                    If this element is present, the bus interface can serve as a master.  This element encapsulates additional information related to its role as master.

                                If this master connects to an addressable bus, this element references the address space it maps to.

                                                If the master's mapping to the physical address space is not zero based, the baseAddress element may be used to indicate the offset. If not specified the offset is 0. The baseAddress is in units of the addressSpace addressUnitBits

                                                    Base of an address space.

                    If this element is present, the bus interface can serve as a slave.

                                If this element is present, it indicates that the bus interface provides a bridge to another master bus interface on the same component.  It has a masterRef attribute which contains the name of the other bus interface.  It also has an opaque attribute to indicate that the bus bridge is opaque.

Any slave interface can bridge to multiple master interfaces, and multiple slave interfaces can bridge to the same master interface.

                                        The name of the master bus interface to which this interface bridges.

                                        If true, then this bridge is opaque; the whole of the address range is mappeed by the bridge and there are no gaps.

                                This reference is used to point the filesets that are associated with this slave port.

Depending on the slave port function, there may be completely different software drivers associated with the different ports. 

                                            Abritray name assigned to the collections of fileSets.

                    If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus.

                    If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

                                Represents a set of remap base addresses.

                                            Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The state attribute indicates the name of the remap state for which this address is valid.

                                                            Name of the state in which this remapped address range is valid

                                            The address range of mirrored slave, expressed as the number of bitsInLAU from the containing busInterface. 

                    If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

                    If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

                    Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The spirit:group element must be specified if monitoring a system interface.

                                Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.

            Group of the different modes a busInterface can take on in an abstractor

                    If this element is present, the bus interface can serve as a master.  This element encapsulates additional information related to its role as master.

                    If this element is present, the bus interface can serve as a slave.

                    If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus.

                    If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

                    If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

                    If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

            Type definition for a busInterface in a component

                    The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes. Bus definition can be found through a reference in this file.

                    Listing of maps between logical ports and physical ports.

                                Maps a component's port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component.

                                            Logical port from abstraction definition

                                                        Bus port name as specified inside the abstraction definition

                                                        Definition of the logical indecies for a vectored port.

                                                                    Defines which logical bit maps to the physical left bit below

                                                                    Defines which logical bit maps to the physical right bit below

                                            Physical port from this component

                                                        Component port name as specified inside the model port section