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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 33

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
        parameter integer DWIDTH = 9,
        parameter integer AWIDTH = 6
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output reg f_full,write_tx,f_empty,
        output reg [DWIDTH-1:0] data_out,
        output reg [AWIDTH-1:0] counter
);
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
        reg block_read;
        reg block_write;
 
        wire [AWIDTH-1:0] wr;
        wire [AWIDTH-1:0] rd;
 
//Write pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        wr_ptr <= {(AWIDTH){1'b0}};
                        block_write <= 1'b0;
                end
                else if(block_write)
                begin
                        if(!wr_en)
                                block_write <= 1'b0;
                end
                else if (wr_en && !f_full)
                begin
                        block_write <= 1'b1;
                        mem[wr_ptr]<=data_in;
                        wr_ptr <= wr;
                end
        end
 
//FULL - EMPTY COUNTER
 
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        f_full <= 1'b0;
                        f_empty<= 1'b1;
                        counter <= {(AWIDTH){1'b0}};
                end
                else
                begin
 
                        if (wr_en && !f_full && !block_write)
                        begin
                                if(rd_en && !f_empty && !block_read)
                                begin
                                        counter <= counter;
                                end
                                else
                                begin
                                        counter <= counter + 6'd1;
                                end
                        end
                        else if(rd_en && !f_empty && !block_read)
                        begin
                                counter <= counter - 6'd1;
                        end
 
                        if(counter == 6'd63)
                        begin
                                f_full <= 1'b1;
                        end
                        else
                        begin
                                f_full <= 1'b0;
                        end
 
                        if(counter == 6'd0)
                        begin
                                f_empty <= 1'b1;
                        end
                        else
                        begin
                                f_empty <= 1'b0;
                        end
 
                end
        end
 
//Read pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        rd_ptr   <= {(AWIDTH){1'b0}};
                        data_out <= 9'd0;
                        write_tx <= 1'b0;
                        block_read <= 1'b0;
                end
                else
                begin
 
                        if(block_read == 1)
                        begin
                                if(!rd_en)
                                        block_read<= 1'b0;
 
                                data_out  <= mem[rd_ptr];
                        end
                        else if(rd_en && !f_empty)
                        begin
                                rd_ptr <= rd;
                                block_read<= 1'b1;
                        end
                        else
                        begin
                                data_out  <= mem[rd_ptr];
                        end
 
                        if(rd_en == 1'b1)
                        begin
                                write_tx<= 1'b0;
                        end
                        else if(counter > 6'd0)
                        begin
                                write_tx<= 1'b1;
                        end
                        else
                                write_tx<= write_tx;
 
                end
        end
 
        //assign f_empty   = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
        assign wr        = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
        assign rd        = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule

Line No.	Rev	Author	Line
1	33	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module fifo_tx`
34			`#(`
35			`parameter integer DWIDTH = 9,`
36			`parameter integer AWIDTH = 6`
37			`)`
38
39			`(`
40			`input clock, reset, wr_en, rd_en,`
41			`input [DWIDTH-1:0] data_in,`
42			`output reg f_full,write_tx,f_empty,`
43			`output reg [DWIDTH-1:0] data_out,`
44			`output reg [AWIDTH-1:0] counter`
45			`);`
46
47			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
48
49			`reg [AWIDTH-1:0] wr_ptr;`
50			`reg [AWIDTH-1:0] rd_ptr;`
51
52			`reg block_read;`
53			`reg block_write;`
54
55			`wire [AWIDTH-1:0] wr;`
56			`wire [AWIDTH-1:0] rd;`
57
58			`//Write pointer`
59			`always@(posedge clock or negedge reset)`
60			`begin`
61			`if (!reset)`
62			`begin`
63			`wr_ptr <= {(AWIDTH){1'b0}};`
64			`block_write <= 1'b0;`
65			`end`
66			`else if(block_write)`
67			`begin`
68			`if(!wr_en)`
69			`block_write <= 1'b0;`
70			`end`
71			`else if (wr_en && !f_full)`
72			`begin`
73			`block_write <= 1'b1;`
74			`mem[wr_ptr]<=data_in;`
75			`wr_ptr <= wr;`
76			`end`
77			`end`
78
79			`//FULL - EMPTY COUNTER`
80
81			`always@(posedge clock or negedge reset)`
82			`begin`
83			`if (!reset)`
84			`begin`
85			`f_full <= 1'b0;`
86			`f_empty<= 1'b1;`
87			`counter <= {(AWIDTH){1'b0}};`
88			`end`
89			`else`
90			`begin`
91
92			`if (wr_en && !f_full && !block_write)`
93			`begin`
94			`if(rd_en && !f_empty && !block_read)`
95			`begin`
96			`counter <= counter;`
97			`end`
98			`else`
99			`begin`
100			`counter <= counter + 6'd1;`
101			`end`
102			`end`
103			`else if(rd_en && !f_empty && !block_read)`
104			`begin`
105			`counter <= counter - 6'd1;`
106			`end`
107
108			`if(counter == 6'd63)`
109			`begin`
110			`f_full <= 1'b1;`
111			`end`
112			`else`
113			`begin`
114			`f_full <= 1'b0;`
115			`end`
116
117			`if(counter == 6'd0)`
118			`begin`
119			`f_empty <= 1'b1;`
120			`end`
121			`else`
122			`begin`
123			`f_empty <= 1'b0;`
124			`end`
125
126			`end`
127			`end`
128
129			`//Read pointer`
130			`always@(posedge clock or negedge reset)`
131			`begin`
132			`if (!reset)`
133			`begin`
134			`rd_ptr <= {(AWIDTH){1'b0}};`
135			`data_out <= 9'd0;`
136			`write_tx <= 1'b0;`
137			`block_read <= 1'b0;`
138			`end`
139			`else`
140			`begin`
141
142			`if(block_read == 1)`
143			`begin`
144			`if(!rd_en)`
145			`block_read<= 1'b0;`
146
147			`data_out <= mem[rd_ptr];`
148			`end`
149			`else if(rd_en && !f_empty)`
150			`begin`
151			`rd_ptr <= rd;`
152			`block_read<= 1'b1;`
153			`end`
154			`else`
155			`begin`
156			`data_out <= mem[rd_ptr];`
157			`end`
158
159			`if(rd_en == 1'b1)`
160			`begin`
161			`write_tx<= 1'b0;`
162			`end`
163			`else if(counter > 6'd0)`
164			`begin`
165			`write_tx<= 1'b1;`
166			`end`
167			`else`
168			`write_tx<= write_tx;`
169
170			`end`
171			`end`
172
173			`//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;`
174			`assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;`
175			`assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;`
176
177			`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 33