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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 34

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1 33 redbear 
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module fifo_tx
34 
#(
35 
        parameter integer DWIDTH = 9,
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        parameter integer AWIDTH = 6
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)
38 
 
39 
(
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        input clock, reset, wr_en, rd_en,
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        input [DWIDTH-1:0] data_in,
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        output reg f_full,write_tx,f_empty,
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        output reg [DWIDTH-1:0] data_out,
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        output reg [AWIDTH-1:0] counter
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);
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47 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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49 
        reg [AWIDTH-1:0] wr_ptr;
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        reg [AWIDTH-1:0] rd_ptr;
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52 
        reg block_read;
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        reg block_write;
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55 
 
56 
//Write pointer
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        always@(posedge clock or negedge reset)
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        begin
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                if (!reset)
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                begin
61 34 redbear 
                        mem[0]  <= {(DWIDTH){1'b0}};
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                        mem[1]  <= {(DWIDTH){1'b0}};
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                        mem[2]  <= {(DWIDTH){1'b0}};
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                        mem[3]  <= {(DWIDTH){1'b0}};
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                        mem[4]  <= {(DWIDTH){1'b0}};
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                        mem[5]  <= {(DWIDTH){1'b0}};
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                        mem[6]  <= {(DWIDTH){1'b0}};
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                        mem[7]  <= {(DWIDTH){1'b0}};
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                        mem[8]  <= {(DWIDTH){1'b0}};
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                        mem[9]  <= {(DWIDTH){1'b0}};
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                        mem[10] <= {(DWIDTH){1'b0}};
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                        mem[11] <= {(DWIDTH){1'b0}};
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                        mem[12] <= {(DWIDTH){1'b0}};
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                        mem[13] <= {(DWIDTH){1'b0}};
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                        mem[14] <= {(DWIDTH){1'b0}};
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                        mem[15] <= {(DWIDTH){1'b0}};
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                        mem[16] <= {(DWIDTH){1'b0}};
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                        mem[17] <= {(DWIDTH){1'b0}};
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                        mem[18] <= {(DWIDTH){1'b0}};
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                        mem[19] <= {(DWIDTH){1'b0}};
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                        mem[20] <= {(DWIDTH){1'b0}};
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                        mem[21] <= {(DWIDTH){1'b0}};
84 
 
85 
                        mem[22] <= {(DWIDTH){1'b0}};
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                        mem[23] <= {(DWIDTH){1'b0}};
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                        mem[24] <= {(DWIDTH){1'b0}};
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                        mem[25] <= {(DWIDTH){1'b0}};
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                        mem[26] <= {(DWIDTH){1'b0}};
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                        mem[27] <= {(DWIDTH){1'b0}};
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                        mem[28] <= {(DWIDTH){1'b0}};
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                        mem[29] <= {(DWIDTH){1'b0}};
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                        mem[30] <= {(DWIDTH){1'b0}};
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                        mem[31] <= {(DWIDTH){1'b0}};
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                        mem[32] <= {(DWIDTH){1'b0}};
96 
 
97 
 
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                        mem[33] <= {(DWIDTH){1'b0}};
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                        mem[34] <= {(DWIDTH){1'b0}};
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                        mem[35] <= {(DWIDTH){1'b0}};
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                        mem[36] <= {(DWIDTH){1'b0}};
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                        mem[37] <= {(DWIDTH){1'b0}};
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                        mem[38] <= {(DWIDTH){1'b0}};
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                        mem[39] <= {(DWIDTH){1'b0}};
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                        mem[40] <= {(DWIDTH){1'b0}};
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                        mem[41] <= {(DWIDTH){1'b0}};
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                        mem[42] <= {(DWIDTH){1'b0}};
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                        mem[43] <= {(DWIDTH){1'b0}};
109 
 
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                        mem[44] <= {(DWIDTH){1'b0}};
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                        mem[45] <= {(DWIDTH){1'b0}};
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                        mem[46] <= {(DWIDTH){1'b0}};
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                        mem[47] <= {(DWIDTH){1'b0}};
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                        mem[48] <= {(DWIDTH){1'b0}};
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                        mem[49] <= {(DWIDTH){1'b0}};
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                        mem[50] <= {(DWIDTH){1'b0}};
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                        mem[51] <= {(DWIDTH){1'b0}};
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                        mem[52] <= {(DWIDTH){1'b0}};
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                        mem[53] <= {(DWIDTH){1'b0}};
120 
                        mem[54] <= {(DWIDTH){1'b0}};
121 
 
122 
                        mem[55] <= {(DWIDTH){1'b0}};
123 
                        mem[56] <= {(DWIDTH){1'b0}};
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                        mem[57] <= {(DWIDTH){1'b0}};
125 
                        mem[58] <= {(DWIDTH){1'b0}};
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                        mem[59] <= {(DWIDTH){1'b0}};
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                        mem[60] <= {(DWIDTH){1'b0}};
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                        mem[61] <= {(DWIDTH){1'b0}};
129 
                        mem[62] <= {(DWIDTH){1'b0}};
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                        mem[63] <= {(DWIDTH){1'b0}};
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132 
                        wr_ptr      <= {(AWIDTH){1'b0}};
133 33 redbear 
                        block_write <= 1'b0;
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                end
135 34 redbear 
                else
136 33 redbear 
                begin
137 34 redbear 
 
138 
                        if(block_write)
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                        begin
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                                if(!wr_en)
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                                begin
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                                        block_write <= 1'b0;
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                                        wr_ptr <= wr_ptr + 6'd1;
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                                end
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                        end
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                        else if (wr_en && !f_full)
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                        begin
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                                block_write <= 1'b1;
149 
                                mem[wr_ptr]<=data_in;
150 
                        end
151 33 redbear 
                end
152 
        end
153 
 
154 
//FULL - EMPTY COUNTER
155 
 
156 
        always@(posedge clock or negedge reset)
157 
        begin
158 
                if (!reset)
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                begin
160 34 redbear 
                        f_full  <= 1'b0;
161 
                        f_empty <= 1'b1;
162 33 redbear 
                        counter <= {(AWIDTH){1'b0}};
163 
                end
164 
                else
165 
                begin
166 
 
167 34 redbear 
                        if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
168 33 redbear 
                        begin
169 34 redbear 
                                counter <= counter;
170 33 redbear 
                        end
171 34 redbear 
                        else if (wr_en && !f_full && !block_write)
172 
                        begin
173 
                                counter <= counter + 6'd1;
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                        end
175 33 redbear 
                        else if(rd_en && !f_empty && !block_read)
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                        begin
177 
                                counter <= counter - 6'd1;
178 
                        end
179 34 redbear 
                        else
180 
                        begin
181 
                                counter <= counter;
182 
                        end
183 33 redbear 
 
184 
                        if(counter == 6'd63)
185 
                        begin
186 
                                f_full <= 1'b1;
187 
                        end
188 
                        else
189 
                        begin
190 
                                f_full <= 1'b0;
191 
                        end
192 
 
193 
                        if(counter == 6'd0)
194 
                        begin
195 
                                f_empty <= 1'b1;
196 
                        end
197 
                        else
198 
                        begin
199 
                                f_empty <= 1'b0;
200 
                        end
201 
 
202 
                end
203 
        end
204 
 
205 
//Read pointer
206 
        always@(posedge clock or negedge reset)
207 
        begin
208 
                if (!reset)
209 
                begin
210 34 redbear 
                        rd_ptr     <= {(AWIDTH){1'b0}};
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                        data_out   <= 9'd0;
212 
                        write_tx   <= 1'b0;
213 33 redbear 
                        block_read <= 1'b0;
214 
                end
215 
                else
216 
                begin
217 
 
218 34 redbear 
                        if(block_read)
219 33 redbear 
                        begin
220 
                                if(!rd_en)
221 34 redbear 
                                begin
222 33 redbear 
                                        block_read<= 1'b0;
223 34 redbear 
                                end
224 33 redbear 
                        end
225 
                        else if(rd_en && !f_empty)
226 
                        begin
227 
                                block_read<= 1'b1;
228 34 redbear 
                                rd_ptr <= rd_ptr+ 6'd1;
229 
 
230 33 redbear 
                        end
231 
 
232 34 redbear 
                        data_out  <= mem[rd_ptr];
233 
 
234 
                        if(rd_en)
235 33 redbear 
                        begin
236 
                                write_tx<= 1'b0;
237 
                        end
238 
                        else if(counter > 6'd0)
239 
                        begin
240 
                                write_tx<= 1'b1;
241 
                        end
242 
                        else
243 
                                write_tx<= write_tx;
244 
 
245 
                end
246 
        end
247 
 
248 
        //assign f_empty   = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
249 34 redbear 
        //assign wr        = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
250 
        //assign rd        = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
251 33 redbear 
 
252 
endmodule

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