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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output reg rx_got_bit,
                        output reg rx_got_null,
                        output reg rx_got_nchar,
                        output reg rx_got_time_code,
                        output reg rx_got_fct,
                        output reg rx_got_fct_fsm,
 
                        output reg [8:0] rx_data_flag,
                        output reg rx_buffer_write,
 
                        output [7:0] rx_time_out,
                        output reg rx_tick_out
                 );
 
 
        reg  [5:0] counter_neg;
        reg control_bit_found;
        reg data_bit_found;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg  [1:0] state_data_process;
        reg  [1:0] next_state_data_process;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        reg parity_received;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [3:0] control_p_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [3:0] control_l_r;
 
        reg [9:0] dta_timec;
        reg [9:0] dta_timec_p;
 
        reg ready_control;
        reg ready_data;
 
        reg ready_control_p;
        reg ready_data_p;
 
        reg ready_control_p_r;
        reg ready_data_p_r;
 
        reg parity_rec_c;
        reg parity_rec_d;
 
        reg rx_error_c;
        reg rx_error_d;
 
        reg posedge_p;
 
        //CLOCK RECOVERY
        assign posedge_clk      = posedge_p;
        assign negedge_clk      = !posedge_p;
 
        assign rx_time_out      = timecode[7:0];
 
        assign rx_error         = rx_error_c | rx_error_d;
 
always@(*)
begin
 
        rx_got_bit = 1'b0;
 
        if(rx_din | rx_sin)
        begin
                rx_got_bit = 1'b1;
        end
end
 
always@(*)
begin
        ready_control    = 1'b0;
        ready_data       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && !posedge_p)
        begin
                ready_control = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && !posedge_p)
        begin
                ready_data       = 1'b1;
        end
end
 
 
always@(*)
begin
        ready_control_p    = 1'b0;
        ready_data_p       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && posedge_p)
        begin
                ready_control_p = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && posedge_p)
        begin
                ready_data_p       = 1'b1;
        end
end
 
always@(*)
begin
        posedge_p = 1'b0;
 
        if(rx_din ^ rx_sin)
        begin
                posedge_p = 1'b1;
        end
        else
        begin
                posedge_p = 1'b0;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_1  <= 1'b0;
                bit_d_3  <= 1'b0;
                bit_d_5  <= 1'b0;
                bit_d_7  <= 1'b0;
                bit_d_9  <= 1'b0;
        end
        else
        begin
                bit_d_1  <= rx_din;
                bit_d_3  <= bit_d_1;
                bit_d_5  <= bit_d_3;
                bit_d_7  <= bit_d_5;
                bit_d_9  <= bit_d_7;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
 
        end
        else
        begin
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1   <= 1'b0;
                bit_c_3   <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0   <= 1'b0;
                bit_c_2   <= 1'b0;
        end
        else
        begin
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_fct        <= 1'b0;
        end
        else
        begin
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
                begin
                        rx_got_fct        <= 1'b1;
                end
                else
                begin
                        rx_got_fct        <= 1'b0;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_null       <= 1'b0;
                rx_got_nchar      <= 1'b0;
                rx_got_time_code  <= 1'b0;
        end
        else
        begin
                if(last_is_data == 1'b1 )
                begin
                        rx_got_nchar      <= 1'b1;
                end
                else if(last_is_timec  == 1'b1)
                begin
                        rx_got_time_code  <= 1'b1;
                end
                else if(last_is_control == 1'b1)
                begin
                        rx_got_null       <= 1'b1;
                end
                else
                begin
                        rx_got_null       <= 1'b0;
                        rx_got_nchar      <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                rx_got_fct_fsm  <=  1'b0;
                ready_control_p_r <= 1'b0;
                ready_data_p_r  <=  1'b0;
 
        end
        else
        begin
 
                if(ready_control || ready_control_p)
                begin
                        if(is_control)
                                ready_control_p_r <= 1'b1;
                        else
                                ready_control_p_r <= 1'b0;
                end
                else
                begin
                        ready_control_p_r <= 1'b0;
                end
 
                if(ready_data || ready_data_p)
                begin
                        if(!is_control)
                                ready_data_p_r <= 1'b1;
                        else
                                ready_data_p_r <= 1'b0;
                end
                else
                begin
                        ready_data_p_r <= 1'b0;
                end
 
                if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
                        rx_got_fct_fsm <= 1'b1;
                else
                        rx_got_fct_fsm <= rx_got_fct_fsm;
        end
end
 
always@(posedge ready_control or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_r               <= 4'd0;
                parity_rec_c            <= 1'b0;
        end
        else
        begin
                control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
                parity_rec_c      <= bit_c_3;
        end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_p_r             <= 4'd0;
 
        end
        else
        begin
                control_p_r       <= control_r;
        end
end
 
 
 
always@(posedge ready_data or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec               <= 10'd0;
                parity_rec_d            <= 1'b0;
        end
        else
        begin
                dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
                parity_rec_d      <= bit_d_9;
        end
end
 
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec_p             <= 10'd0;
        end
        else
        begin
                dta_timec_p  <= dta_timec;
        end
end
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                rx_error_d <= 1'b0;
        end
        else
        begin
                if(last_is_control)
                begin
                        if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
                        begin
                                rx_error_d <= 1'b1;
                        end
                end
                else if(last_is_data)
                begin
                        if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
                        begin
                                rx_error_d <= 1'b1;
                        end
                end
        end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                rx_error_c <= 1'b0;
 
        end
        else
        begin
                if(last_is_control)
                begin
                        if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
                        begin
                                rx_error_c <= 1'b1;
                        end
                end
                else if(last_is_data)
                begin
                        if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
                        begin
                                rx_error_c <= 1'b1;
                        end
                end
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_buffer_write <= 1'b0;
                rx_tick_out     <= 1'b0;
        end
        else
        begin
 
                if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)
                begin
                        if(last_is_timec == 1'b1)
                        begin
                                rx_tick_out  <= 1'b1;
                        end
                        else if(last_is_data == 1'b1)
                        begin
                                rx_buffer_write <= 1'b1;
                        end
                        else if(last_is_control == 1'b1)
                        begin
                                if(control[2:0] == 3'd6)
                                begin
                                        rx_buffer_write <= 1'b1;
                                end
                                else if(control[2:0] == 3'd5)
                                begin
                                        rx_buffer_write <= 1'b1;
                                end
                        end
                end
                else
                begin
                        rx_buffer_write <= 1'b0;
                        rx_tick_out     <= 1'b0;
                end
        end
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                is_control <= 1'b0;
                control_bit_found <= 1'b0;
                counter_neg[5:0]  <= 6'd1;
        end
        else
        begin
 
                control_bit_found <= rx_din;
 
                case(counter_neg)
                6'd1:
                begin
                        counter_neg[5:0]  <=  6'd2;
                end
                6'd2:
                begin
                        if(control_bit_found == 1'b1)
                        begin
                                is_control  <= 1'b1;
                        end
                        else
                        begin
                                is_control  <= 1'b0;
                        end
 
                        counter_neg[5:0] <= 6'd4;
                end
                6'd4:
                begin
                        if(is_control == 1'b1)
                        begin
                                counter_neg[5:0] <= 6'd2;
                                is_control <= 1'b0;
                        end
                        else
                        begin
                                counter_neg[5:0] <= 6'd8;
                        end
                end
                6'd8:
                begin
                        counter_neg[5:0] <= 6'd16;
                end
                6'd16:
                begin
                        counter_neg[5:0] <= 6'd32;
                end
                6'd32:
                begin
                        is_control <= 1'b0;
                        counter_neg[5:0] <= 6'd2;
                end
                default:
                begin
                        is_control <= is_control;
                        counter_neg[5:0] <= counter_neg[5:0];
                end
                endcase
 
        end
end
 
always@(*)
begin
 
        next_state_data_process = state_data_process;
 
        case(state_data_process)
        2'd0:
        begin
                if(ready_control_p_r || ready_data_p_r)
                begin
                        next_state_data_process = 2'd1;
                end
                else
                begin
                        next_state_data_process = 2'd0;
                end
        end
        2'd1:
        begin
                next_state_data_process = 2'd0;
        end
        default:
        begin
                next_state_data_process = 2'd0;
        end
        endcase
end
 
 
always@(posedge negedge_clk or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                control_l_r      <= 4'd0;
                control          <= 4'd0;
                data             <=  10'd0;
 
                last_is_control  <=  1'b0;
                last_is_data     <=  1'b0;
                last_is_timec    <=  1'b0;
 
                rx_data_flag     <=  9'd0;
                timecode         <=  10'd0;
 
                state_data_process <= 2'd0;
        end
        else
        begin
 
                state_data_process <= next_state_data_process;
 
                case(state_data_process)
                2'd0:
                begin
 
                        if(ready_control_p_r)
                        begin
                                control          <= control_p_r;
                                control_l_r      <= control;
 
                                if(control_p_r[2:0] == 3'd6)
                                begin
                                        rx_data_flag <= 9'd257;
                                end
                                else if(control_p_r[2:0] == 3'd5)
                                begin
                                        rx_data_flag <= 9'd256;
                                end
                                else
                                begin
                                        rx_data_flag <= rx_data_flag;
                                end
 
                                last_is_control          <= 1'b1;
                                last_is_data             <= 1'b0;
                                last_is_timec            <= 1'b0;
 
                        end
                        else if(ready_data_p_r)
                        begin
                                if(control[2:0] != 3'd7)
                                begin
                                        data            <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                        rx_data_flag    <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                        last_is_control         <=1'b0;
                                        last_is_data            <=1'b1;
                                        last_is_timec           <=1'b0;
                                end
                                else if(control[2:0] == 3'd7)
                                begin
                                        timecode     <=  {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                        last_is_control         <= 1'b0;
                                        last_is_data            <= 1'b0;
                                        last_is_timec           <= 1'b1;
                                end
                        end
                        else
                        begin
                                timecode        <= timecode;
                        end
 
                end
                2'd1:
                begin
                                rx_data_flag    <= rx_data_flag;
                                timecode        <= timecode;
                end
                default:
                begin
                                rx_data_flag    <= rx_data_flag;
                                timecode        <= timecode;
 
                end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42	37	redbear	`output rx_error,`
43	5	redbear
44	33	redbear	`output reg rx_got_bit,`
45	25	redbear	`output reg rx_got_null,`
46			`output reg rx_got_nchar,`
47			`output reg rx_got_time_code,`
48	23	redbear	`output reg rx_got_fct,`
49	25	redbear	`output reg rx_got_fct_fsm,`
50	5	redbear
51	19	redbear	`output reg [8:0] rx_data_flag,`
52			`output reg rx_buffer_write,`
53	5	redbear
54	25	redbear	`output [7:0] rx_time_out,`
55	19	redbear	`output reg rx_tick_out`
56	5	redbear	`);`
57
58
59	33	redbear	`reg [5:0] counter_neg;`
60	25	redbear	`reg control_bit_found;`
61	33	redbear	`reg data_bit_found;`
62	5	redbear
63			`wire posedge_clk;`
64			`wire negedge_clk;`
65
66	37	redbear	`reg [1:0] state_data_process;`
67			`reg [1:0] next_state_data_process;`
68
69	14	redbear	`reg bit_c_0;//N`
70			`reg bit_c_1;//P`
71			`reg bit_c_2;//N`
72			`reg bit_c_3;//P`
73	5	redbear
74	14	redbear	`reg bit_d_0;//N`
75			`reg bit_d_1;//P`
76			`reg bit_d_2;//N`
77			`reg bit_d_3;//P`
78			`reg bit_d_4;//N`
79			`reg bit_d_5;//P`
80			`reg bit_d_6;//N`
81			`reg bit_d_7;//P`
82			`reg bit_d_8;//N`
83			`reg bit_d_9;//P`
84	5	redbear
85	14	redbear	`reg is_control;`
86	37	redbear	`reg parity_received;`
87	5	redbear
88	14	redbear	`reg last_is_control;`
89			`reg last_is_data;`
90			`reg last_is_timec;`
91	5	redbear
92	14	redbear	`reg [3:0] control;`
93	23	redbear	`reg [3:0] control_r;`
94	33	redbear	`reg [3:0] control_p_r;`
95	14	redbear	`reg [9:0] data;`
96			`reg [9:0] timecode;`
97	5	redbear
98	14	redbear	`reg [3:0] control_l_r;`
99	5	redbear
100	23	redbear	`reg [9:0] dta_timec;`
101	33	redbear	`reg [9:0] dta_timec_p;`
102	23	redbear
103	33	redbear	`reg ready_control;`
104			`reg ready_data;`
105	23	redbear
106	33	redbear	`reg ready_control_p;`
107			`reg ready_data_p;`
108
109			`reg ready_control_p_r;`
110			`reg ready_data_p_r;`
111
112	37	redbear	`reg parity_rec_c;`
113			`reg parity_rec_d;`
114
115			`reg rx_error_c;`
116			`reg rx_error_d;`
117
118	33	redbear	`reg posedge_p;`
119	25	redbear
120	14	redbear	`//CLOCK RECOVERY`
121	33	redbear	`assign posedge_clk = posedge_p;`
122			`assign negedge_clk = !posedge_p;`
123	5	redbear
124	25	redbear	`assign rx_time_out = timecode[7:0];`
125	5	redbear
126	37	redbear	`assign rx_error = rx_error_c \| rx_error_d;`
127
128	33	redbear	`always@(*)`
129			`begin`
130	5	redbear
131	33	redbear	`rx_got_bit = 1'b0;`
132
133			`if(rx_din \| rx_sin)`
134			`begin`
135			`rx_got_bit = 1'b1;`
136			`end`
137			`end`
138
139			`always@(*)`
140			`begin`
141			`ready_control = 1'b0;`
142			`ready_data = 1'b0;`
143
144			`if(counter_neg[5:0] == 6'd4 && !posedge_p)`
145			`begin`
146			`ready_control = 1'b1;`
147			`end`
148			`else if(counter_neg[5:0] == 6'd32 && !posedge_p)`
149			`begin`
150			`ready_data = 1'b1;`
151			`end`
152			`end`
153
154
155			`always@(*)`
156			`begin`
157			`ready_control_p = 1'b0;`
158			`ready_data_p = 1'b0;`
159
160			`if(counter_neg[5:0] == 6'd4 && posedge_p)`
161			`begin`
162			`ready_control_p = 1'b1;`
163			`end`
164			`else if(counter_neg[5:0] == 6'd32 && posedge_p)`
165			`begin`
166			`ready_data_p = 1'b1;`
167			`end`
168			`end`
169
170			`always@(*)`
171			`begin`
172			`posedge_p = 1'b0;`
173
174	34	redbear	`if(rx_din ^ rx_sin)`
175	33	redbear	`begin`
176			`posedge_p = 1'b1;`
177			`end`
178			`else`
179			`begin`
180			`posedge_p = 1'b0;`
181			`end`
182			`end`
183
184	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
185	5	redbear	`begin`
186	14	redbear
187			`if(!rx_resetn)`
188	5	redbear	`begin`
189	25	redbear	`bit_d_1 <= 1'b0;`
190			`bit_d_3 <= 1'b0;`
191			`bit_d_5 <= 1'b0;`
192			`bit_d_7 <= 1'b0;`
193			`bit_d_9 <= 1'b0;`
194	5	redbear	`end`
195			`else`
196			`begin`
197	25	redbear	`bit_d_1 <= rx_din;`
198			`bit_d_3 <= bit_d_1;`
199			`bit_d_5 <= bit_d_3;`
200			`bit_d_7 <= bit_d_5;`
201			`bit_d_9 <= bit_d_7;`
202	5	redbear	`end`
203	14	redbear
204	5	redbear	`end`
205
206	14	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
207	5	redbear	`begin`
208	14	redbear
209			`if(!rx_resetn)`
210	5	redbear	`begin`
211	14	redbear	`bit_d_0 <= 1'b0;`
212			`bit_d_2 <= 1'b0;`
213			`bit_d_4 <= 1'b0;`
214			`bit_d_6 <= 1'b0;`
215			`bit_d_8 <= 1'b0;`
216	25	redbear
217	5	redbear	`end`
218			`else`
219			`begin`
220	14	redbear	`bit_d_0 <= rx_din;`
221			`bit_d_2 <= bit_d_0;`
222			`bit_d_4 <= bit_d_2;`
223			`bit_d_6 <= bit_d_4;`
224			`bit_d_8 <= bit_d_6;`
225	23	redbear	`end`
226			`end`
227	14	redbear
228	25	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
229	23	redbear	`begin`
230	25	redbear
231			`if(!rx_resetn)`
232	23	redbear	`begin`
233	25	redbear	`bit_c_1 <= 1'b0;`
234			`bit_c_3 <= 1'b0;`
235	23	redbear	`end`
236	25	redbear	`else`
237			`begin`
238			`bit_c_1 <= rx_din;`
239			`bit_c_3 <= bit_c_1;`
240			`end`
241
242	23	redbear	`end`
243
244	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
245	23	redbear	`begin`
246
247	25	redbear	`if(!rx_resetn)`
248	23	redbear	`begin`
249	25	redbear	`bit_c_0 <= 1'b0;`
250			`bit_c_2 <= 1'b0;`
251	23	redbear	`end`
252	25	redbear	`else`
253	23	redbear	`begin`
254	25	redbear	`bit_c_0 <= rx_din;`
255			`bit_c_2 <= bit_c_0;`
256	23	redbear	`end`
257			`end`
258
259			`always@(posedge negedge_clk or negedge rx_resetn)`
260			`begin`
261
262			`if(!rx_resetn)`
263			`begin`
264	37	redbear	`rx_got_fct <= 1'b0;`
265	23	redbear	`end`
266			`else`
267	33	redbear	`begin`
268			`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`
269	5	redbear	`begin`
270	38	redbear	`rx_got_fct <= 1'b1;`
271	5	redbear	`end`
272			`else`
273			`begin`
274	38	redbear	`rx_got_fct <= 1'b0;`
275	5	redbear	`end`
276	25	redbear	`end`
277			`end`
278
279			`always@(posedge negedge_clk or negedge rx_resetn)`
280			`begin`
281
282			`if(!rx_resetn)`
283			`begin`
284			`rx_got_null <= 1'b0;`
285			`rx_got_nchar <= 1'b0;`
286			`rx_got_time_code <= 1'b0;`
287			`end`
288			`else`
289			`begin`
290	33	redbear	`if(last_is_data == 1'b1 )`
291	5	redbear	`begin`
292	25	redbear	`rx_got_nchar <= 1'b1;`
293	5	redbear	`end`
294	33	redbear	`else if(last_is_timec == 1'b1)`
295	5	redbear	`begin`
296	25	redbear	`rx_got_time_code <= 1'b1;`
297	5	redbear	`end`
298	33	redbear	`else if(last_is_control == 1'b1)`
299	5	redbear	`begin`
300	25	redbear	`rx_got_null <= 1'b1;`
301	5	redbear	`end`
302	25	redbear	`else`
303			`begin`
304	33	redbear	`rx_got_null <= 1'b0;`
305			`rx_got_nchar <= 1'b0;`
306			`rx_got_time_code <= 1'b0;`
307	25	redbear	`end`
308	5	redbear	`end`
309			`end`
310
311	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
312	5	redbear	`begin`
313	25	redbear	`if(!rx_resetn)`
314			`begin`
315	33	redbear	`rx_got_fct_fsm <= 1'b0;`
316			`ready_control_p_r <= 1'b0;`
317			`ready_data_p_r <= 1'b0;`
318
319	25	redbear	`end`
320			`else`
321			`begin`
322	5	redbear
323	33	redbear	`if(ready_control \|\| ready_control_p)`
324			`begin`
325			`if(is_control)`
326			`ready_control_p_r <= 1'b1;`
327	37	redbear	`else`
328			`ready_control_p_r <= 1'b0;`
329	33	redbear	`end`
330			`else`
331			`begin`
332			`ready_control_p_r <= 1'b0;`
333			`end`
334
335			`if(ready_data \|\| ready_data_p)`
336			`begin`
337			`if(!is_control)`
338			`ready_data_p_r <= 1'b1;`
339	37	redbear	`else`
340			`ready_data_p_r <= 1'b0;`
341	33	redbear	`end`
342			`else`
343			`begin`
344			`ready_data_p_r <= 1'b0;`
345			`end`
346
347			`if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)`
348	25	redbear	`rx_got_fct_fsm <= 1'b1;`
349			`else`
350			`rx_got_fct_fsm <= rx_got_fct_fsm;`
351			`end`
352			`end`
353
354			`always@(posedge ready_control or negedge rx_resetn )`
355			`begin`
356	14	redbear	`if(!rx_resetn)`
357	5	redbear	`begin`
358	25	redbear	`control_r <= 4'd0;`
359	37	redbear	`parity_rec_c <= 1'b0;`
360	25	redbear	`end`
361			`else`
362			`begin`
363	37	redbear	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
364			`parity_rec_c <= bit_c_3;`
365	25	redbear	`end`
366			`end`
367	23	redbear
368	33	redbear	`always@(posedge ready_control_p or negedge rx_resetn )`
369			`begin`
370			`if(!rx_resetn)`
371			`begin`
372			`control_p_r <= 4'd0;`
373	37	redbear
374	33	redbear	`end`
375			`else`
376			`begin`
377	37	redbear	`control_p_r <= control_r;`
378	33	redbear	`end`
379			`end`
380	5	redbear
381	33	redbear
382
383	25	redbear	`always@(posedge ready_data or negedge rx_resetn )`
384			`begin`
385			`if(!rx_resetn)`
386			`begin`
387			`dta_timec <= 10'd0;`
388	37	redbear	`parity_rec_d <= 1'b0;`
389	25	redbear	`end`
390			`else`
391			`begin`
392	37	redbear	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
393			`parity_rec_d <= bit_d_9;`
394	25	redbear	`end`
395			`end`
396	5	redbear
397	33	redbear
398			`always@(posedge ready_data_p or negedge rx_resetn )`
399			`begin`
400			`if(!rx_resetn)`
401			`begin`
402			`dta_timec_p <= 10'd0;`
403			`end`
404			`else`
405			`begin`
406	37	redbear	`dta_timec_p <= dta_timec;`
407	33	redbear	`end`
408			`end`
409
410	39	redbear	`always@(posedge ready_data_p or negedge rx_resetn )`
411	37	redbear	`begin`
412
413	39	redbear	`if(!rx_resetn)`
414	37	redbear	`begin`
415	39	redbear	`rx_error_d <= 1'b0;`
416	37	redbear	`end`
417	39	redbear	`else`
418	37	redbear	`begin`
419	39	redbear	`if(last_is_control)`
420	37	redbear	`begin`
421	39	redbear	`if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)`
422			`begin`
423			`rx_error_d <= 1'b1;`
424			`end`
425	37	redbear	`end`
426	39	redbear	`else if(last_is_data)`
427			`begin`
428			`if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)`
429			`begin`
430			`rx_error_d <= 1'b1;`
431			`end`
432			`end`
433	37	redbear	`end`
434			`end`
435
436	39	redbear	`always@(posedge ready_control_p or negedge rx_resetn )`
437	37	redbear	`begin`
438
439	39	redbear	`if(!rx_resetn)`
440	37	redbear	`begin`
441	39	redbear	`rx_error_c <= 1'b0;`
442
443	37	redbear	`end`
444	39	redbear	`else`
445	37	redbear	`begin`
446	39	redbear	`if(last_is_control)`
447	37	redbear	`begin`
448	39	redbear	`if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)`
449			`begin`
450			`rx_error_c <= 1'b1;`
451			`end`
452	37	redbear	`end`
453	39	redbear	`else if(last_is_data)`
454			`begin`
455			`if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)`
456			`begin`
457			`rx_error_c <= 1'b1;`
458			`end`
459			`end`
460	37	redbear	`end`
461	39	redbear
462	37	redbear	`end`
463
464	33	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
465			`begin`
466	38	redbear
467			`if(!rx_resetn)`
468			`begin`
469			`rx_buffer_write <= 1'b0;`
470			`rx_tick_out <= 1'b0;`
471			`end`
472			`else`
473			`begin`
474	33	redbear
475	38	redbear	`if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)`
476			`begin`
477			`if(last_is_timec == 1'b1)`
478			`begin`
479			`rx_tick_out <= 1'b1;`
480			`end`
481			`else if(last_is_data == 1'b1)`
482			`begin`
483			`rx_buffer_write <= 1'b1;`
484			`end`
485			`else if(last_is_control == 1'b1)`
486			`begin`
487			`if(control[2:0] == 3'd6)`
488			`begin`
489			`rx_buffer_write <= 1'b1;`
490			`end`
491			`else if(control[2:0] == 3'd5)`
492			`begin`
493			`rx_buffer_write <= 1'b1;`
494			`end`
495			`end`
496			`end`
497			`else`
498			`begin`
499			`rx_buffer_write <= 1'b0;`
500			`rx_tick_out <= 1'b0;`

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