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jeaander |
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# File: sport_top.tcl
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# Generated on: Fri Feb 20 13:49:57 2015
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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set need_to_close_project 0
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set make_assignments 1
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# Check that the right project is open
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if {[is_project_open]} {
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if {[string compare $quartus(project) "sport_top"]} {
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puts "Project sport_top is not open"
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set make_assignments 0
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}
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} else {
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# Only open if not already open
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if {[project_exists sport_top]} {
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project_open -revision sport_top sport_top
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} else {
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project_new -revision sport_top sport_top
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}
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set need_to_close_project 1
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}
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# Make assignments
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if {$make_assignments} {
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set_global_assignment -name FAMILY "Cyclone IV GX"
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set_global_assignment -name DEVICE EP4CGX15BF14C6
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:24:50 FEBRUARY 20, 2015"
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set_global_assignment -name LAST_QUARTUS_VERSION 14.0
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set_global_assignment -name VERILOG_FILE ../../rtl/verilog/wb_interface.v
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set_global_assignment -name VERILOG_FILE ../../rtl/verilog/sport_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/verilog/sport_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/verilog/fifos.v
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment IOBANK_3 -to wb_dat_o[0]
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set_location_assignment IOBANK_3 -to DRxPRI
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set_location_assignment IOBANK_3A -to DRxSEC
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set_location_assignment IOBANK_4 -to DTxPRI
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set_location_assignment IOBANK_6 -to DTxSEC
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set_location_assignment IOBANK_6 -to RSCLKx
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set_location_assignment IOBANK_7 -to TFSx
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set_location_assignment IOBANK_8 -to TRSx
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set_location_assignment PIN_B11 -to TSCLKx
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# Commit assignments
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export_assignments
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# Close project
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if {$need_to_close_project} {
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project_close
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}
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}
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