URL https://opencores.org/ocsvn/sport/sport/trunk

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[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [iseconfig/] [sport_top.projectmgr] - Blame information for rev 7

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         2
         /Automatic `includes
         /sport_top C:|Users|jeffA|Desktop|rtl|sport|trunk|rtl|verilog|sport_top.v
      
      
         sport_top (C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000cc000000020000000000000000000000000200000064ffffffff000000810000000300000002000000cc0000000100000003000000000000000100000003
      true
      sport_top (C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v)
   
   
      
         1
         Design Utilities
      
      
      0
      0
      
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001c20000000100000000
      false
      fifos.v
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
      false
      work
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design
         Synthesize - XST
      
      
         Implement Design
      
      4
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000
      false
      Implement Design
   
   000000ff00000000000000020000011b0000011b01000000050100000002
   Implementation


Line No.	Rev	Author	Line
1	7	jeaander
2
3
4
5
6
7
8
9			`2`
10			/Automatic `includes
11			`/sport_top C:\|Users\|jeffA\|Desktop\|rtl\|sport\|trunk\|rtl\|verilog\|sport_top.v`
12
13
14			`sport_top (C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v)`
15
16			`0`
17			`0`
18			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000cc000000020000000000000000000000000200000064ffffffff000000810000000300000002000000cc0000000100000003000000000000000100000003`
19			`true`
20			`sport_top (C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v)`
21
22
23
24			`1`
25			`Design Utilities`
26
27
28			`0`
29			`0`
30
31			`false`
32
33
34
35
36			`1`
37
38
39			`0`
40			`0`
41			`000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001c20000000100000000`
42			`false`
43			`fifos.v`
44
45
46
47			`1`
48			`work`
49
50
51			`0`
52			`0`
53			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000`
54			`false`
55			`work`
56
57
58
59			`1`
60			`Configure Target Device`
61			`Design Utilities`
62			`Implement Design`
63			`Synthesize - XST`
64
65
66			`Implement Design`
67
68			`4`
69			`0`
70			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000`
71			`false`
72			`Implement Design`
73
74			`000000ff00000000000000020000011b0000011b01000000050100000002`
75			`Implementation`
76

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[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [iseconfig/] [sport_top.projectmgr] - Blame information for rev 7