URL
https://opencores.org/ocsvn/sport/sport/trunk
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Rev |
Author |
Line |
| 1 |
7 |
jeaander |
Release 14.7 - ngc2edif P.20131013 (nt64)
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| 2 |
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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| 3 |
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Reading design sport_top.ngc ...
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| 4 |
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WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.
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| 5 |
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Processing design ...
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| 6 |
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Preping design's networks ...
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| 7 |
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Preping design's macros ...
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| 8 |
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WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on block
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| 9 |
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sport_top is not reconstructed, because there are some missing bus signals.
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| 10 |
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WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on block
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| 11 |
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sport_top is not reconstructed, because there are some missing bus signals.
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| 12 |
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finished :Prep
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| 13 |
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Writing EDIF netlist file sport_top.edif ...
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| 14 |
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ngc2edif: Total memory usage is 79372 kilobytes
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| 15 |
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| 16 |
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Release 14.7 - ngc2edif P.20131013 (nt64)
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| 17 |
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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| 18 |
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Reading design sport_top.ngc ...
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| 19 |
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WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.
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| 20 |
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Processing design ...
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| 21 |
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Preping design's networks ...
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| 22 |
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Preping design's macros ...
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| 23 |
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WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on block
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| 24 |
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sport_top is not reconstructed, because there are some missing bus signals.
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| 25 |
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WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on block
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| 26 |
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sport_top is not reconstructed, because there are some missing bus signals.
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| 27 |
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finished :Prep
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| 28 |
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Writing EDIF netlist file sport_top.edif ...
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| 29 |
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ngc2edif: Total memory usage is 79052 kilobytes
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| 30 |
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