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jeaander |
Release 14.7 par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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JEFFA-PC:: Fri Feb 20 14:09:00 2015
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par -w -intstyle ise -ol high -t 1 sport_top_map.ncd sport_top.ncd
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sport_top.pcf
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Constraints file: sport_top.pcf.
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Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"sport_top" is an NCD, version 3.2, device xc3s700an, package fgg484, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.42 2013-10-13".
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Design Summary Report:
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Number of External IOBs 76 out of 372 20%
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Number of External Input IOBs 34
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Number of External Input IBUFs 34
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Number of LOCed External Input IBUFs 2 out of 34 5%
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Number of External Output IOBs 42
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Number of External Output IOBs 42
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Number of LOCed External Output IOBs 5 out of 42 11%
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Number of External Bidir IOBs 0
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Number of BUFGMUXs 3 out of 24 12%
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Number of Slices 41 out of 5888 1%
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Number of SLICEMs 0 out of 2944 0%
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Overall effort level (-ol): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 5 secs
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Finished initial Timing Analysis. REAL time: 5 secs
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WARNING:Par:288 - The signal DRxSEC_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal DRxPRI_IBUF has no load. PAR will not attempt to route this signal.
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Starting Placer
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Total REAL time at the beginning of Placer: 6 secs
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Total CPU time at the beginning of Placer: 2 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:6b5992a5) REAL time: 8 secs
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Phase 2.7 Design Feasibility Check
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INFO:Place:834 - Only a subset of IOs are locked. Out of 42 IOs, 5 are locked and 37 are not locked. If you would like
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
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Phase 2.7 Design Feasibility Check (Checksum:6b5992a5) REAL time: 9 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:6b5992a5) REAL time: 9 secs
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Phase 4.2 Initial Clock and IO Placement
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.....
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Phase 4.2 Initial Clock and IO Placement (Checksum:a0a71119) REAL time: 12 secs
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Phase 5.30 Global Clock Region Assignment
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Phase 5.30 Global Clock Region Assignment (Checksum:a0a71119) REAL time: 12 secs
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Phase 6.36 Local Placement Optimization
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Phase 6.36 Local Placement Optimization (Checksum:a0a71119) REAL time: 12 secs
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Phase 7.3 Local Placement Optimization
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......
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Phase 7.3 Local Placement Optimization (Checksum:a69910d4) REAL time: 14 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:a69910d4) REAL time: 14 secs
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Phase 9.8 Global Placement
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....
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..
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Phase 9.8 Global Placement (Checksum:f6127ce3) REAL time: 14 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:f6127ce3) REAL time: 14 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:f44e05d2) REAL time: 16 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:f44e05d2) REAL time: 16 secs
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Total REAL time to Placer completion: 16 secs
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Total CPU time to Placer completion: 10 secs
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Writing design to file sport_top.ncd
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Starting Router
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Phase 1 : 308 unrouted; REAL time: 21 secs
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Phase 2 : 277 unrouted; REAL time: 21 secs
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Phase 3 : 38 unrouted; REAL time: 21 secs
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Phase 4 : 38 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
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Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
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Updating file: sport_top.ncd with current fully routed design.
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Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
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Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
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Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
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Total REAL time to Router completion: 22 secs
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Total CPU time to Router completion: 15 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| wb_clk_i_BUFGP | BUFGMUX_X1Y1| No | 13 | 0.053 | 1.090 |
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+---------------------+--------------+------+------+------------+-------------+
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| TSCLKx_OBUF | BUFGMUX_X1Y10| No | 13 | 0.076 | 1.070 |
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+---------------------+--------------+------+------+------------+-------------+
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| RSCLKx_OBUF | BUFGMUX_X1Y0| No | 1 | 0.000 | 0.994 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Number of Timing Constraints that were not applied: 1
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 1 | SETUP | 6.860ns| 3.140ns| 0| 0
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| MINLOWPULSE | 6.796ns| 3.204ns| 0| 0
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----------------------------------------------------------------------------------------------------------
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TS_txclk = PERIOD TIMEGRP "txclk" 20 ns H | SETUP | 15.365ns| 4.635ns| 0| 0
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IGH 50% | HOLD | 1.314ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns H | MINPERIOD | 18.398ns| 1.602ns| 0| 0
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IGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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Generating Pad Report.
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All signals are completely routed.
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WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
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Total REAL time to PAR completion: 24 secs
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Total CPU time to PAR completion: 16 secs
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Peak Memory Usage: 357 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 4
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Number of info messages: 1
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Writing design to file sport_top.ncd
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PAR done!
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