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jeaander |
//! **************************************************************************
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// Written by: Map P.20131013 on Fri Feb 20 14:08:53 2015
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//! **************************************************************************
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SCHEMATIC START;
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COMP "RFSx" LOCATE = SITE "A7" LEVEL 1;
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COMP "RSCLKx" LOCATE = SITE "A6" LEVEL 1;
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COMP "TFSx" LOCATE = SITE "A8" LEVEL 1;
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COMP "DRxSEC" LOCATE = SITE "A3" LEVEL 1;
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COMP "DRxPRI" LOCATE = SITE "A2" LEVEL 1;
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COMP "DTxSEC" LOCATE = SITE "A5" LEVEL 1;
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COMP "DTxPRI" LOCATE = SITE "A4" LEVEL 1;
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TIMEGRP txclk = BEL "txsampleCnt_tx_0" BEL "txsampleCnt_tx_1" BEL
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"txsampleCnt_tx_2" BEL "txsampleCnt_tx_3" BEL "txsampleCnt_tx_4" BEL
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"txpacketCnt_tx_0" BEL "txpacketCnt_tx_1" BEL "txpacketCnt_tx_2" BEL
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"txpacketCnt_tx_3" BEL "txpacketCnt_tx_4" BEL "txpacketCnt_tx_5" BEL
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"txpacketCnt_tx_6" BEL "txpacketCnt_tx_7" BEL "txpacketCnt_tx_8" BEL
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"txpacketCnt_tx_9" BEL "tx_start_tx" BEL "txfs_rnm0" BEL
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"state_FSM_FFd1" BEL "state_FSM_FFd2" BEL "TSCLKx" BEL
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"TSCLKx_OBUF_BUFG.GCLKMUX" BEL "TSCLKx_OBUF_BUFG";
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TIMEGRP rxclk = BEL "rxfs_rnm0" BEL "RSCLKx" BEL "RSCLKx_OBUF_BUFG.GCLKMUX"
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BEL "RSCLKx_OBUF_BUFG";
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TIMEGRP wb_clk_i = BEL "wb_interface/rxreg_0" BEL "wb_interface/rxreg_15" BEL
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"wb_interface/rxreg_17" BEL "wb_interface/rxreg_20" BEL
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"wb_interface/txreg_20" BEL "wb_interface/txreg_17" BEL
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"wb_interface/txreg_16" BEL "wb_interface/txreg_14" BEL
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"wb_interface/txreg_13" BEL "wb_interface/txreg_12" BEL
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"wb_interface/txreg_11" BEL "wb_interface/txreg_10" BEL
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"wb_interface/txreg_9" BEL "wb_interface/txreg_8" BEL
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"wb_interface/txreg_7" BEL "wb_interface/txreg_6" BEL
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"wb_interface/txreg_5" BEL "wb_interface/txreg_4" BEL
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"wb_interface/txreg_3" BEL "wb_interface/txreg_2" BEL
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"wb_interface/txreg_1" BEL "wb_interface/txreg_0" BEL
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"wb_interface/ack" BEL "wb_interface/rty" BEL
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"wb_clk_i_BUFGP/BUFG.GCLKMUX" BEL "wb_clk_i_BUFGP/BUFG";
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TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;
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TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;
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TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;
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SCHEMATIC END;
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