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jeaander |
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twDebug*, twFoot?, twClientInfo?)>
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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OFFSET |
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OFFSETIN |
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OFFSETOUT |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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twSimpleMinPath CDATA #IMPLIED>
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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]>
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Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
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| 333 |
|
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-n 3 -fastpaths -xml sport_top.twx sport_top.ncd -o sport_top.twr sport_top.pcf
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| 334 |
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-ucf sport_top.ucf
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| 335 |
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| 336 |
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sport_top.ncdsport_top.ncdsport_top.pcfsport_top.pcfxc3s700an-4PRODUCTION 1.42 2013-10-133INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;00000001.602Component Switching Limit Checks: TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;12800006004.635Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F2), 10 paths
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| 337 |
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15.365txpacketCnt_tx_7state_FSM_FFd24.672-0.03720.0000.000txpacketCnt_tx_7state_FSM_FFd23SLICE_X4Y60.CLKTSCLKx_OBUFSLICE_X4Y60.XQTcko0.631txpacketCnt_tx<7>txpacketCnt_tx_7SLICE_X5Y51.G3net21.234txpacketCnt_tx<7>SLICE_X5Y51.COUTTopcyg1.178Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_lut<3>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CINnet10.000Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XBTcinxb0.296Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2net10.531Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd22.9071.7654.672TSCLKx_OBUF62.237.815.387txpacketCnt_tx_3state_FSM_FFd24.634-0.02120.0000.000txpacketCnt_tx_3state_FSM_FFd24SLICE_X4Y58.CLKTSCLKx_OBUFSLICE_X4Y58.XQTcko0.631txpacketCnt_tx<3>txpacketCnt_tx_3SLICE_X5Y50.G2net21.066txpacketCnt_tx<3>SLICE_X5Y50.COUTTopcyg1.178Mcompar_state_cmp_eq0001_cy<1>Mcompar_state_cmp_eq0001_lut<1>Mcompar_state_cmp_eq0001_cy<1>SLICE_X5Y51.CINnet10.000Mcompar_state_cmp_eq0001_cy<1>SLICE_X5Y51.COUTTbyp0.130Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_cy<2>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CINnet10.000Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XBTcinxb0.296Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2net10.531Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd23.0371.5974.634TSCLKx_OBUF65.534.515.400txpacketCnt_tx_4state_FSM_FFd24.637-0.03720.0000.000txpacketCnt_tx_4state_FSM_FFd23SLICE_X4Y61.CLKTSCLKx_OBUFSLICE_X4Y61.YQTcko0.676txpacketCnt_tx<5>txpacketCnt_tx_4SLICE_X5Y51.F3net21.137txpacketCnt_tx<4>SLICE_X5Y51.COUTTopcyf1.195Mcompar_state_cmp_eq0001_cy<3>Mcompar_state_cmp_eq0001_lut<2>Mcompar_state_cmp_eq0001_cy<2>Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.CINnet10.000Mcompar_state_cmp_eq0001_cy<3>SLICE_X5Y52.XBTcinxb0.296Mcompar_state_cmp_eq0001_cy<4>Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.F2net10.531Mcompar_state_cmp_eq0001_cy<4>SLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd22.9691.6684.637TSCLKx_OBUF64.036.0Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F3), 5 paths
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| 338 |
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15.427txsampleCnt_tx_4state_FSM_FFd24.5690.00420.0000.000txsampleCnt_tx_4state_FSM_FFd24SLICE_X4Y55.CLKTSCLKx_OBUFSLICE_X4Y55.XQTcko0.631txsampleCnt_tx<4>txsampleCnt_tx_4SLICE_X5Y53.G2net20.903txsampleCnt_tx<4>SLICE_X5Y53.YTilo0.648state_FSM_FFd1-In_bdd2state_FSM_FFd1-In51SLICE_X5Y53.F4net10.044state_FSM_FFd1-In51/OSLICE_X5Y53.XTilo0.643state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4net20.148state_FSM_FFd1-In_bdd2SLICE_X4Y53.YTilo0.707state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3net10.043state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd23.4311.1384.569TSCLKx_OBUF75.124.915.471txsampleCnt_tx_1state_FSM_FFd24.5250.00420.0000.000txsampleCnt_tx_1state_FSM_FFd24SLICE_X5Y54.CLKTSCLKx_OBUFSLICE_X5Y54.XQTcko0.591txsampleCnt_tx<1>txsampleCnt_tx_1SLICE_X4Y54.F1net40.579txsampleCnt_tx<1>SLICE_X4Y54.XTilo0.692txsampleCnt_tx<2>state_FSM_FFd1-In41_SW0SLICE_X5Y53.F3net10.320N21SLICE_X5Y53.XTilo0.643state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4net20.148state_FSM_FFd1-In_bdd2SLICE_X4Y53.YTilo0.707state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3net10.043state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd23.4351.0904.525TSCLKx_OBUF75.924.115.651txsampleCnt_tx_3state_FSM_FFd24.3450.00420.0000.000txsampleCnt_tx_3state_FSM_FFd24SLICE_X5Y55.CLKTSCLKx_OBUFSLICE_X5Y55.XQTcko0.591txsampleCnt_tx<3>txsampleCnt_tx_3SLICE_X5Y53.G4net30.719txsampleCnt_tx<3>SLICE_X5Y53.YTilo0.648state_FSM_FFd1-In_bdd2state_FSM_FFd1-In51SLICE_X5Y53.F4net10.044state_FSM_FFd1-In51/OSLICE_X5Y53.XTilo0.643state_FSM_FFd1-In_bdd2state_FSM_FFd1-In31SLICE_X4Y53.G4net20.148state_FSM_FFd1-In_bdd2SLICE_X4Y53.YTilo0.707state_FSM_FFd2state_FSM_FFd1-In21_SW0SLICE_X4Y53.F3net10.043state_FSM_FFd1-In21_SW0/OSLICE_X4Y53.CLKTfck0.802state_FSM_FFd2state_FSM_FFd2-In11state_FSM_FFd23.3910.9544.345TSCLKx_OBUF78.022.0Paths for end point txpacketCnt_tx_9 (SLICE_X4Y62.F2), 10 paths
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| 339 |
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15.504txpacketCnt_tx_1txpacketCnt_tx_94.4670.02920.0000.000txpacketCnt_tx_1txpacketCnt_tx_96SLICE_X4Y59.CLKTSCLKx_OBUFSLICE_X4Y59.XQTcko0.631txpacketCnt_tx<1>txpacketCnt_tx_1SLICE_X5Y58.G1net20.528txpacketCnt_tx<1>SLICE_X5Y58.COUTTopcyg1.178txpacketCnt_tx_addsub0000<0>txpacketCnt_tx<1>_rtMadd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.COUTTbyp0.130txpacketCnt_tx_addsub0000<2>Madd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUTTbyp0.130txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUTTbyp0.130txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.YTciny0.864txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2net10.074txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLKTfck0.802txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_93.8650.6024.467TSCLKx_OBUF86.513.515.560txpacketCnt_tx_0txpacketCnt_tx_94.4110.02920.0000.000txpacketCnt_tx_0txpacketCnt_tx_96SLICE_X4Y59.CLKTSCLKx_OBUFSLICE_X4Y59.YQTcko0.676txpacketCnt_tx<1>txpacketCnt_tx_0SLICE_X5Y58.F4net20.410txpacketCnt_tx<0>SLICE_X5Y58.COUTTopcyf1.195txpacketCnt_tx_addsub0000<0>Madd_txpacketCnt_tx_addsub0000_lut<0>_INV_0Madd_txpacketCnt_tx_addsub0000_cy<0>Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<1>SLICE_X5Y59.COUTTbyp0.130txpacketCnt_tx_addsub0000<2>Madd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUTTbyp0.130txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUTTbyp0.130txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.YTciny0.864txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2net10.074txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLKTfck0.802txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_93.9270.4844.411TSCLKx_OBUF89.011.015.564txpacketCnt_tx_2txpacketCnt_tx_94.4070.02920.0000.000txpacketCnt_tx_2txpacketCnt_tx_95SLICE_X4Y58.CLKTSCLKx_OBUFSLICE_X4Y58.YQTcko0.676txpacketCnt_tx<3>txpacketCnt_tx_2SLICE_X5Y59.F3net20.536txpacketCnt_tx<2>SLICE_X5Y59.COUTTopcyf1.195txpacketCnt_tx_addsub0000<2>txpacketCnt_tx<2>_rtMadd_txpacketCnt_tx_addsub0000_cy<2>Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<3>SLICE_X5Y60.COUTTbyp0.130txpacketCnt_tx_addsub0000<4>Madd_txpacketCnt_tx_addsub0000_cy<4>Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<5>SLICE_X5Y61.COUTTbyp0.130txpacketCnt_tx_addsub0000<6>Madd_txpacketCnt_tx_addsub0000_cy<6>Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.CINnet10.000Madd_txpacketCnt_tx_addsub0000_cy<7>SLICE_X5Y62.YTciny0.864txpacketCnt_tx_addsub0000<8>Madd_txpacketCnt_tx_addsub0000_cy<8>Madd_txpacketCnt_tx_addsub0000_xor<9>SLICE_X4Y62.F2net10.074txpacketCnt_tx_addsub0000<9>SLICE_X4Y62.CLKTfck0.802txpacketCnt_tx<9>txpacketCnt_tx_mux0000<9>1txpacketCnt_tx_93.7970.6104.407TSCLKx_OBUF86.213.8Hold Paths: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;
|
| 340 |
|
|
Paths for end point txsampleCnt_tx_1 (SLICE_X5Y54.F4), 1 path
|
| 341 |
|
|
1.314txsampleCnt_tx_1txsampleCnt_tx_11.3140.0000.0000.000txsampleCnt_tx_1txsampleCnt_tx_11SLICE_X5Y54.CLKTSCLKx_OBUFSLICE_X5Y54.XQTcko0.473txsampleCnt_tx<1>txsampleCnt_tx_1SLICE_X5Y54.F4net40.375txsampleCnt_tx<1>SLICE_X5Y54.CLKTckf0.466txsampleCnt_tx<1>txsampleCnt_tx_mux0000<1>1txsampleCnt_tx_10.9390.3751.314TSCLKx_OBUF71.528.5Paths for end point txsampleCnt_tx_0 (SLICE_X5Y54.G4), 1 path
|
| 342 |
|
|
1.363state_FSM_FFd2txsampleCnt_tx_01.367-0.0040.0000.000state_FSM_FFd2txsampleCnt_tx_01SLICE_X4Y53.CLKTSCLKx_OBUFSLICE_X4Y53.XQTcko0.505state_FSM_FFd2state_FSM_FFd2SLICE_X5Y54.G4net180.392state_FSM_FFd2SLICE_X5Y54.CLKTckg0.470txsampleCnt_tx<1>txsampleCnt_tx_mux0000<0>1txsampleCnt_tx_00.9750.3921.367TSCLKx_OBUF71.328.7Paths for end point txsampleCnt_tx_3 (SLICE_X5Y55.F3), 1 path
|
| 343 |
|
|
1.418state_FSM_FFd2txsampleCnt_tx_31.422-0.0040.0000.000state_FSM_FFd2txsampleCnt_tx_31SLICE_X4Y53.CLKTSCLKx_OBUFSLICE_X4Y53.XQTcko0.505state_FSM_FFd2state_FSM_FFd2SLICE_X5Y55.F3net180.451state_FSM_FFd2SLICE_X5Y55.CLKTckf0.466txsampleCnt_tx<3>txsampleCnt_tx_mux0000<3>1txsampleCnt_tx_30.9710.4511.422TSCLKx_OBUF68.331.7Component Switching Limit Checks: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;2200002203.204Paths for end point wb_interface/rxreg_20 (SLICE_X1Y54.CE), 1 path
|
| 344 |
|
|
6.860wb_interface/rxreg_20wb_interface/rxreg_203.1400.00010.0000.000wb_interface/rxreg_20wb_interface/rxreg_201SLICE_X1Y54.CLKwb_clk_i_BUFGPSLICE_X1Y54.XQTcko0.591wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4net10.404wb_interface/rxreg<20>SLICE_X0Y54.YTilo0.707wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y54.CEnet21.127wb_interface/rxreg_and0000SLICE_X1Y54.CLKTceck0.311wb_interface/rxreg<20>wb_interface/rxreg_201.6091.5313.140wb_clk_i_BUFGP51.248.8Paths for end point wb_interface/rxreg_17 (SLICE_X1Y54.CE), 1 path
|
| 345 |
|
|
6.860wb_interface/rxreg_20wb_interface/rxreg_173.1400.00010.0000.000wb_interface/rxreg_20wb_interface/rxreg_171SLICE_X1Y54.CLKwb_clk_i_BUFGPSLICE_X1Y54.XQTcko0.591wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4net10.404wb_interface/rxreg<20>SLICE_X0Y54.YTilo0.707wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y54.CEnet21.127wb_interface/rxreg_and0000SLICE_X1Y54.CLKTceck0.311wb_interface/rxreg<20>wb_interface/rxreg_171.6091.5313.140wb_clk_i_BUFGP51.248.8Paths for end point wb_interface/rxreg_15 (SLICE_X1Y50.CE), 1 path
|
| 346 |
|
|
6.861wb_interface/rxreg_20wb_interface/rxreg_153.140-0.00110.0000.000wb_interface/rxreg_20wb_interface/rxreg_151SLICE_X1Y54.CLKwb_clk_i_BUFGPSLICE_X1Y54.XQTcko0.591wb_interface/rxreg<20>wb_interface/rxreg_20SLICE_X0Y54.G4net10.404wb_interface/rxreg<20>SLICE_X0Y54.YTilo0.707wb_interface/wb_dat_rdbkwb_interface/rxreg_and00001SLICE_X1Y50.CEnet21.127wb_interface/rxreg_and0000SLICE_X1Y50.CLKTceck0.311wb_interface/rxreg<15>wb_interface/rxreg_151.6091.5313.140wb_clk_i_BUFGP51.248.8Hold Paths: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;
|
| 347 |
|
|
Paths for end point wb_interface/txreg_20 (SLICE_X0Y56.CE), 1 path
|
| 348 |
|
|
1.912wb_interface/txreg_20wb_interface/txreg_201.9120.0000.0000.000wb_interface/txreg_20wb_interface/txreg_201SLICE_X0Y56.CLKwb_clk_i_BUFGPSLICE_X0Y56.XQTcko0.505wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1net10.377wb_interface/txreg<20>SLICE_X1Y56.XTilo0.514wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X0Y56.CEnet90.516wb_interface/txreg_and0000SLICE_X0Y56.CLKTckce0.000wb_interface/txreg<20>wb_interface/txreg_201.0190.8931.912wb_clk_i_BUFGP53.346.7Paths for end point wb_interface/txreg_17 (SLICE_X0Y56.CE), 1 path
|
| 349 |
|
|
1.912wb_interface/txreg_20wb_interface/txreg_171.9120.0000.0000.000wb_interface/txreg_20wb_interface/txreg_171SLICE_X0Y56.CLKwb_clk_i_BUFGPSLICE_X0Y56.XQTcko0.505wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1net10.377wb_interface/txreg<20>SLICE_X1Y56.XTilo0.514wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X0Y56.CEnet90.516wb_interface/txreg_and0000SLICE_X0Y56.CLKTckce0.000wb_interface/txreg<20>wb_interface/txreg_171.0190.8931.912wb_clk_i_BUFGP53.346.7Paths for end point wb_interface/txreg_5 (SLICE_X3Y47.CE), 1 path
|
| 350 |
|
|
1.944wb_interface/txreg_20wb_interface/txreg_52.094-0.1500.0000.000wb_interface/txreg_20wb_interface/txreg_51SLICE_X0Y56.CLKwb_clk_i_BUFGPSLICE_X0Y56.XQTcko0.505wb_interface/txreg<20>wb_interface/txreg_20SLICE_X1Y56.F1net10.377wb_interface/txreg<20>SLICE_X1Y56.XTilo0.514wb_interface/txreg_and0000wb_interface/txreg_and00001SLICE_X3Y47.CEnet90.698wb_interface/txreg_and0000SLICE_X3Y47.CLKTckce0.000wb_interface/txreg<5>wb_interface/txreg_51.0191.0752.094wb_clk_i_BUFGP48.751.3Component Switching Limit Checks: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;0txclktxclk4.635wb_clk_iwb_clk_i3.140000015001404.635215.750Fri Feb 20 14:09:29 2015 TraceTrace Settings
|
| 351 |
|
|
|
| 352 |
|
|
Peak Memory Usage: 188 MB
|
| 353 |
|
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|
