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[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [sport_top.unroutes] - Blame information for rev 7

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Line No. Rev Author Line
1 7 jeaander
Release 14.7 - par P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Fri Feb 20 14:09:24 2015
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All signals are completely routed.
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WARNING:ParHelpers:361 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC
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   warnings.
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   DRxPRI_IBUF
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   DRxSEC_IBUF
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