| 1 |
7 |
jeaander |
Release 14.7 Map P.20131013 (nt64)
|
| 2 |
|
|
Xilinx Mapping Report File for Design 'sport_top'
|
| 3 |
|
|
|
| 4 |
|
|
Design Information
|
| 5 |
|
|
------------------
|
| 6 |
|
|
Command Line : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -pr
|
| 7 |
|
|
off -c 100 -o sport_top_map.ncd sport_top.ngd sport_top.pcf
|
| 8 |
|
|
Target Device : xc3s700an
|
| 9 |
|
|
Target Package : fgg484
|
| 10 |
|
|
Target Speed : -4
|
| 11 |
|
|
Mapper Version : spartan3a -- $Revision: 1.55 $
|
| 12 |
|
|
Mapped Date : Fri Feb 20 14:08:41 2015
|
| 13 |
|
|
|
| 14 |
|
|
Design Summary
|
| 15 |
|
|
--------------
|
| 16 |
|
|
Number of errors: 0
|
| 17 |
|
|
Number of warnings: 2
|
| 18 |
|
|
Logic Utilization:
|
| 19 |
|
|
Number of Slice Flip Flops: 42 out of 11,776 1%
|
| 20 |
|
|
Number of 4 input LUTs: 42 out of 11,776 1%
|
| 21 |
|
|
Logic Distribution:
|
| 22 |
|
|
Number of occupied Slices: 41 out of 5,888 1%
|
| 23 |
|
|
Number of Slices containing only related logic: 41 out of 41 100%
|
| 24 |
|
|
Number of Slices containing unrelated logic: 0 out of 41 0%
|
| 25 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic.
|
| 26 |
|
|
Total Number of 4 input LUTs: 51 out of 11,776 1%
|
| 27 |
|
|
Number used as logic: 42
|
| 28 |
|
|
Number used as a route-thru: 9
|
| 29 |
|
|
|
| 30 |
|
|
The Slice Logic Distribution report is not meaningful if the design is
|
| 31 |
|
|
over-mapped for a non-slice resource or if Placement fails.
|
| 32 |
|
|
|
| 33 |
|
|
Number of bonded IOBs: 76 out of 372 20%
|
| 34 |
|
|
IOB Flip Flops: 2
|
| 35 |
|
|
Number of BUFGMUXs: 3 out of 24 12%
|
| 36 |
|
|
|
| 37 |
|
|
Average Fanout of Non-Clock Nets: 2.40
|
| 38 |
|
|
|
| 39 |
|
|
Peak Memory Usage: 342 MB
|
| 40 |
|
|
Total REAL time to MAP completion: 15 secs
|
| 41 |
|
|
Total CPU time to MAP completion: 4 secs
|
| 42 |
|
|
|
| 43 |
|
|
NOTES:
|
| 44 |
|
|
|
| 45 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 46 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 47 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 48 |
|
|
the best timing performance.
|
| 49 |
|
|
|
| 50 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 51 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 52 |
|
|
related logic packing.
|
| 53 |
|
|
|
| 54 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 55 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 56 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 57 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 58 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 59 |
|
|
of your design.
|
| 60 |
|
|
|
| 61 |
|
|
Table of Contents
|
| 62 |
|
|
-----------------
|
| 63 |
|
|
Section 1 - Errors
|
| 64 |
|
|
Section 2 - Warnings
|
| 65 |
|
|
Section 3 - Informational
|
| 66 |
|
|
Section 4 - Removed Logic Summary
|
| 67 |
|
|
Section 5 - Removed Logic
|
| 68 |
|
|
Section 6 - IOB Properties
|
| 69 |
|
|
Section 7 - RPMs
|
| 70 |
|
|
Section 8 - Guide Report
|
| 71 |
|
|
Section 9 - Area Group and Partition Summary
|
| 72 |
|
|
Section 10 - Timing Report
|
| 73 |
|
|
Section 11 - Configuration String Information
|
| 74 |
|
|
Section 12 - Control Set Information
|
| 75 |
|
|
Section 13 - Utilization by Hierarchy
|
| 76 |
|
|
|
| 77 |
|
|
Section 1 - Errors
|
| 78 |
|
|
------------------
|
| 79 |
|
|
|
| 80 |
|
|
Section 2 - Warnings
|
| 81 |
|
|
--------------------
|
| 82 |
|
|
WARNING:PhysDesignRules:367 - The signal is incomplete. The signal
|
| 83 |
|
|
does not drive any load pins in the design.
|
| 84 |
|
|
WARNING:PhysDesignRules:367 - The signal is incomplete. The signal
|
| 85 |
|
|
does not drive any load pins in the design.
|
| 86 |
|
|
|
| 87 |
|
|
Section 3 - Informational
|
| 88 |
|
|
-------------------------
|
| 89 |
|
|
INFO:LIT:243 - Logical network wb_dat_i<31> has no load.
|
| 90 |
|
|
INFO:LIT:395 - The above info message is repeated 14 more times for the
|
| 91 |
|
|
following (max. 5 shown):
|
| 92 |
|
|
wb_dat_i<30>,
|
| 93 |
|
|
wb_dat_i<29>,
|
| 94 |
|
|
wb_dat_i<28>,
|
| 95 |
|
|
wb_dat_i<27>,
|
| 96 |
|
|
wb_dat_i<26>
|
| 97 |
|
|
To see the details of these info messages, please use the -detail switch.
|
| 98 |
|
|
INFO:MapLib:562 - No environment variables are currently set.
|
| 99 |
|
|
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
| 100 |
|
|
rate limited output drivers. The delay on speed critical single ended outputs
|
| 101 |
|
|
can be dramatically reduced by designating them as fast outputs.
|
| 102 |
|
|
|
| 103 |
|
|
Section 4 - Removed Logic Summary
|
| 104 |
|
|
---------------------------------
|
| 105 |
|
|
2 block(s) optimized away
|
| 106 |
|
|
|
| 107 |
|
|
Section 5 - Removed Logic
|
| 108 |
|
|
-------------------------
|
| 109 |
|
|
|
| 110 |
|
|
Optimized Block(s):
|
| 111 |
|
|
TYPE BLOCK
|
| 112 |
|
|
GND XST_GND
|
| 113 |
|
|
VCC XST_VCC
|
| 114 |
|
|
|
| 115 |
|
|
To enable printing of redundant blocks removed and signals merged, set the
|
| 116 |
|
|
detailed map report option and rerun map.
|
| 117 |
|
|
|
| 118 |
|
|
Section 6 - IOB Properties
|
| 119 |
|
|
--------------------------
|
| 120 |
|
|
|
| 121 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 122 |
|
|
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND |
|
| 123 |
|
|
| | | | | Term | Strength | Rate | | | Delay | |
|
| 124 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 125 |
|
|
| DRxPRI | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 126 |
|
|
| DRxSEC | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 127 |
|
|
| DTxPRI | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 128 |
|
|
| DTxSEC | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 129 |
|
|
| RFSx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 130 |
|
|
| RSCLKx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 131 |
|
|
| TFSx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 132 |
|
|
| TSCLKx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 133 |
|
|
| rx_int | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 134 |
|
|
| rxclk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 135 |
|
|
| txclk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 136 |
|
|
| wb_ack_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF1 | | 0 / 0 | 3STATE |
|
| 137 |
|
|
| wb_adr_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 138 |
|
|
| wb_adr_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 139 |
|
|
| wb_adr_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 140 |
|
|
| wb_adr_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 141 |
|
|
| wb_adr_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 142 |
|
|
| wb_adr_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 143 |
|
|
| wb_clk_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 144 |
|
|
| wb_cyc_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 145 |
|
|
| wb_dat_i<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 146 |
|
|
| wb_dat_i<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 147 |
|
|
| wb_dat_i<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 148 |
|
|
| wb_dat_i<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 149 |
|
|
| wb_dat_i<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 150 |
|
|
| wb_dat_i<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 151 |
|
|
| wb_dat_i<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 152 |
|
|
| wb_dat_i<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 153 |
|
|
| wb_dat_i<8> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 154 |
|
|
| wb_dat_i<9> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 155 |
|
|
| wb_dat_i<10> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 156 |
|
|
| wb_dat_i<11> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 157 |
|
|
| wb_dat_i<12> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 158 |
|
|
| wb_dat_i<13> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 159 |
|
|
| wb_dat_i<14> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 160 |
|
|
| wb_dat_i<15> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 161 |
|
|
| wb_dat_i<16> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 162 |
|
|
| wb_dat_i<17> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 163 |
|
|
| wb_dat_i<20> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 164 |
|
|
| wb_dat_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 165 |
|
|
| wb_dat_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 166 |
|
|
| wb_dat_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 167 |
|
|
| wb_dat_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 168 |
|
|
| wb_dat_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 169 |
|
|
| wb_dat_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 170 |
|
|
| wb_dat_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 171 |
|
|
| wb_dat_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 172 |
|
|
| wb_dat_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 173 |
|
|
| wb_dat_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 174 |
|
|
| wb_dat_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 175 |
|
|
| wb_dat_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 176 |
|
|
| wb_dat_o<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 177 |
|
|
| wb_dat_o<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 178 |
|
|
| wb_dat_o<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 179 |
|
|
| wb_dat_o<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 180 |
|
|
| wb_dat_o<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 181 |
|
|
| wb_dat_o<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 182 |
|
|
| wb_dat_o<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 183 |
|
|
| wb_dat_o<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 184 |
|
|
| wb_dat_o<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 185 |
|
|
| wb_dat_o<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 186 |
|
|
| wb_dat_o<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 187 |
|
|
| wb_dat_o<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 188 |
|
|
| wb_dat_o<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 189 |
|
|
| wb_dat_o<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 190 |
|
|
| wb_dat_o<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 191 |
|
|
| wb_dat_o<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 192 |
|
|
| wb_dat_o<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 193 |
|
|
| wb_dat_o<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 194 |
|
|
| wb_dat_o<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 195 |
|
|
| wb_dat_o<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 196 |
|
|
| wb_err_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | 3STATE |
|
| 197 |
|
|
| wb_rst_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 198 |
|
|
| wb_rty_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF1 | | 0 / 0 | 3STATE |
|
| 199 |
|
|
| wb_stb_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 200 |
|
|
| wb_we_i | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
|
| 201 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 202 |
|
|
|
| 203 |
|
|
Section 7 - RPMs
|
| 204 |
|
|
----------------
|
| 205 |
|
|
|
| 206 |
|
|
Section 8 - Guide Report
|
| 207 |
|
|
------------------------
|
| 208 |
|
|
Guide not run on this design.
|
| 209 |
|
|
|
| 210 |
|
|
Section 9 - Area Group and Partition Summary
|
| 211 |
|
|
--------------------------------------------
|
| 212 |
|
|
|
| 213 |
|
|
Partition Implementation Status
|
| 214 |
|
|
-------------------------------
|
| 215 |
|
|
|
| 216 |
|
|
No Partitions were found in this design.
|
| 217 |
|
|
|
| 218 |
|
|
-------------------------------
|
| 219 |
|
|
|
| 220 |
|
|
Area Group Information
|
| 221 |
|
|
----------------------
|
| 222 |
|
|
|
| 223 |
|
|
No area groups were found in this design.
|
| 224 |
|
|
|
| 225 |
|
|
----------------------
|
| 226 |
|
|
|
| 227 |
|
|
Section 10 - Timing Report
|
| 228 |
|
|
--------------------------
|
| 229 |
|
|
This design was not run using timing mode.
|
| 230 |
|
|
|
| 231 |
|
|
Section 11 - Configuration String Details
|
| 232 |
|
|
-----------------------------------------
|
| 233 |
|
|
Use the "-detail" map option to print out Configuration Strings
|
| 234 |
|
|
|
| 235 |
|
|
Section 12 - Control Set Information
|
| 236 |
|
|
------------------------------------
|
| 237 |
|
|
No control set information for this architecture.
|
| 238 |
|
|
|
| 239 |
|
|
Section 13 - Utilization by Hierarchy
|
| 240 |
|
|
-------------------------------------
|
| 241 |
|
|
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
