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ghutchis |
/*! \author Guy Hutchison
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* \brief Top level for bridge example
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*
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* 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock
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* Port macros contain all packet buffering, and ring interface to communicate
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* with other port macros.
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* FIB block receives requests from all ports and sends results back to the
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* same port containing forwarding information.
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*/
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module bridge_ex2
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(input clk, //% 125 Mhz system clock
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input reset, //% Active high system reset
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input gmii_rx_clk_0, // To p0 of port_macro.v
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input gmii_rx_clk_1, // To p1 of port_macro.v
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input gmii_rx_clk_2, // To p2 of port_macro.v
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input gmii_rx_clk_3, // To p3 of port_macro.v
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input gmii_rx_dv_0, // To p0 of port_macro.v
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input gmii_rx_dv_1, // To p1 of port_macro.v
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input gmii_rx_dv_2, // To p2 of port_macro.v
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input gmii_rx_dv_3, // To p3 of port_macro.v
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input [7:0] gmii_rxd_0, // To p0 of port_macro.v
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input [7:0] gmii_rxd_1, // To p1 of port_macro.v
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input [7:0] gmii_rxd_2, // To p2 of port_macro.v
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input [7:0] gmii_rxd_3, // To p3 of port_macro.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output gmii_tx_en_0, // From p0 of port_macro.v
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output gmii_tx_en_1, // From p1 of port_macro.v
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output gmii_tx_en_2, // From p2 of port_macro.v
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output gmii_tx_en_3, // From p3 of port_macro.v
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output [7:0] gmii_txd_0, // From p0 of port_macro.v
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output [7:0] gmii_txd_1, // From p1 of port_macro.v
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output [7:0] gmii_txd_2, // From p2 of port_macro.v
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output [7:0] gmii_txd_3 // From p3 of port_macro.v
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// End of automatics
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);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [(`NUM_PORTS)-1:0] drf_drdy; // From control0 of control_pipe.v
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wire [95:0] drf_page_list; // From p0 of port_macro.v, ...
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wire [3:0] drf_srdy; // From p0 of port_macro.v, ...
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wire [`LL_PG_ASZ-1:0] f2d_data_0; // From control0 of control_pipe.v
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wire [`LL_PG_ASZ-1:0] f2d_data_1; // From control0 of control_pipe.v
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wire [`LL_PG_ASZ-1:0] f2d_data_2; // From control0 of control_pipe.v
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wire [`LL_PG_ASZ-1:0] f2d_data_3; // From control0 of control_pipe.v
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wire [3:0] f2d_drdy; // From p0 of port_macro.v, ...
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wire [3:0] f2d_srdy; // From control0 of control_pipe.v
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wire [(`NUM_PORTS)-1:0] lnp_drdy; // From control0 of control_pipe.v
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wire [99:0] lnp_pnp; // From p0 of port_macro.v, ...
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wire [3:0] lnp_srdy; // From p0 of port_macro.v, ...
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wire [(`NUM_PORTS)-1:0] par_drdy; // From control0 of control_pipe.v
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wire [3:0] par_srdy; // From p0 of port_macro.v, ...
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wire [3:0] parr_drdy; // From p0 of port_macro.v, ...
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wire [(`LL_PG_ASZ)-1:0] parr_page; // From control0 of control_pipe.v
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wire [(`NUM_PORTS)-1:0] parr_srdy; // From control0 of control_pipe.v
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wire [`PBR_SZ-1:0] pbra_data_0; // From p0 of port_macro.v
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wire [`PBR_SZ-1:0] pbra_data_1; // From p1 of port_macro.v
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wire [`PBR_SZ-1:0] pbra_data_2; // From p2 of port_macro.v
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wire [`PBR_SZ-1:0] pbra_data_3; // From p3 of port_macro.v
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wire [3:0] pbra_drdy; // From pktbuf of packet_buffer.v
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wire [3:0] pbra_srdy; // From p0 of port_macro.v, ...
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wire [`PBR_SZ-1:0] pbrd_data_0; // From p0 of port_macro.v
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wire [`PBR_SZ-1:0] pbrd_data_1; // From p1 of port_macro.v
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wire [`PBR_SZ-1:0] pbrd_data_2; // From p2 of port_macro.v
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wire [`PBR_SZ-1:0] pbrd_data_3; // From p3 of port_macro.v
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wire [3:0] pbrd_drdy; // From pktbuf of packet_buffer.v
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wire [3:0] pbrd_srdy; // From p0 of port_macro.v, ...
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wire [`PFW_SZ-1:0] pbrr_data; // From pktbuf of packet_buffer.v
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wire [3:0] pbrr_drdy; // From p0 of port_macro.v, ...
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wire [3:0] pbrr_srdy; // From pktbuf of packet_buffer.v
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wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_0;// From p0 of port_macro.v
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wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_1;// From p1 of port_macro.v
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wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_2;// From p2 of port_macro.v
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wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_3;// From p3 of port_macro.v
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wire [`NUM_PORTS-1:0] pm2f_drdy; // From control0 of control_pipe.v
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wire [3:0] pm2f_srdy; // From p0 of port_macro.v, ...
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wire [(`NUM_PORTS)-1:0] rlp_drdy; // From control0 of control_pipe.v
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wire [47:0] rlp_rd_page; // From p0 of port_macro.v, ...
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wire [3:0] rlp_srdy; // From p0 of port_macro.v, ...
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wire [(`LL_PG_ASZ+1)-1:0] rlpr_data; // From control0 of control_pipe.v
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wire [3:0] rlpr_drdy; // From p0 of port_macro.v, ...
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wire [(`NUM_PORTS)-1:0] rlpr_srdy; // From control0 of control_pipe.v
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// End of automatics
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/* port_macro AUTO_TEMPLATE
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(
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.clk (clk),
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.reset (reset),
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.p2f_srdy (p2f_srdy[@]),
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.p2f_drdy (p2f_drdy[@]),
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.fli_srdy (flo_srdy[@]),
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.fli_drdy (flo_drdy[@]),
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.fli_data (flo_data),
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.drf_srdy (drf_srdy[@]),
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.drf_drdy (drf_drdy[@]),
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.f2d_srdy (f2d_srdy[@]),
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.f2d_drdy (f2d_drdy[@]),
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.par_srdy (par_srdy[@]),
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.par_drdy (par_drdy[@]),
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.parr_srdy (parr_srdy[@]),
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.parr_drdy (parr_drdy[@]),
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.parr_page (parr_page[`LL_PG_ASZ-1:0]),
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.lnp_srdy (lnp_srdy[@]),
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.lnp_drdy (lnp_drdy[@]),
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.rlp_srdy (rlp_srdy[@]),
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.rlp_drdy (rlp_drdy[@]),
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.rlpr_srdy (rlpr_srdy[@]),
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.rlpr_drdy (rlpr_drdy[@]),
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.rlpr_data (rlpr_data[`LL_PG_ASZ:0]),
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.pbrr_data (pbrr_data[`PFW_SZ-1:0]),
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// page size is 12 bits, use 24 bits for each drf port, 25 bits for link port
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.drf_page_list (drf_page_list[@"(- (* (+ @ 1) 24) 1)":@"(* @ 24)"]),
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.lnp_pnp (lnp_pnp[@"(- (* (+ @ 1) 25) 1)":@"(* @ 25)"]),
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// page address size is 12 bits
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.rlp_rd_page (rlp_rd_page[@"(- (* (+ @ 1) 12) 1)":@"(* @ 12)"]),
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.pm2f_srdy (pm2f_srdy[@]),
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.pm2f_drdy (pm2f_drdy[@]),
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.pbra_srdy (pbra_srdy[@]),
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.pbra_drdy (pbra_drdy[@]),
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.pbrd_srdy (pbrd_srdy[@]),
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.pbrd_drdy (pbrd_drdy[@]),
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.pbrr_srdy (pbrr_srdy[@]),
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.pbrr_drdy (pbrr_drdy[@]),
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.\(.*\) (\1_@[]),
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);
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*/
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port_macro #(0) p0
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(/*AUTOINST*/
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// Outputs
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.drf_page_list (drf_page_list[23:0]), // Templated
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.drf_srdy (drf_srdy[0]), // Templated
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.f2d_drdy (f2d_drdy[0]), // Templated
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.gmii_tx_en (gmii_tx_en_0), // Templated
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.gmii_txd (gmii_txd_0[7:0]), // Templated
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.lnp_pnp (lnp_pnp[24:0]), // Templated
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.lnp_srdy (lnp_srdy[0]), // Templated
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.par_srdy (par_srdy[0]), // Templated
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.parr_drdy (parr_drdy[0]), // Templated
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.pbra_data (pbra_data_0[`PBR_SZ-1:0]), // Templated
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.pbra_srdy (pbra_srdy[0]), // Templated
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.pbrd_data (pbrd_data_0[`PBR_SZ-1:0]), // Templated
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.pbrd_srdy (pbrd_srdy[0]), // Templated
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.pbrr_drdy (pbrr_drdy[0]), // Templated
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.pm2f_data (pm2f_data_0[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
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.pm2f_srdy (pm2f_srdy[0]), // Templated
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.rlp_rd_page (rlp_rd_page[11:0]), // Templated
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.rlp_srdy (rlp_srdy[0]), // Templated
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.rlpr_drdy (rlpr_drdy[0]), // Templated
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// Inputs
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.clk (clk), // Templated
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.reset (reset), // Templated
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.drf_drdy (drf_drdy[0]), // Templated
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.f2d_data (f2d_data_0[`LL_PG_ASZ-1:0]), // Templated
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.f2d_srdy (f2d_srdy[0]), // Templated
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.gmii_rx_clk (gmii_rx_clk_0), // Templated
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.gmii_rx_dv (gmii_rx_dv_0), // Templated
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.gmii_rxd (gmii_rxd_0[7:0]), // Templated
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.lnp_drdy (lnp_drdy[0]), // Templated
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.par_drdy (par_drdy[0]), // Templated
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.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated
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.parr_srdy (parr_srdy[0]), // Templated
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.pbra_drdy (pbra_drdy[0]), // Templated
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.pbrd_drdy (pbrd_drdy[0]), // Templated
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.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated
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.pbrr_srdy (pbrr_srdy[0]), // Templated
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.pm2f_drdy (pm2f_drdy[0]), // Templated
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.rlp_drdy (rlp_drdy[0]), // Templated
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.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated
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.rlpr_srdy (rlpr_srdy[0])); // Templated
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port_macro #(1) p1
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(/*AUTOINST*/
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// Outputs
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.drf_page_list (drf_page_list[47:24]), // Templated
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.drf_srdy (drf_srdy[1]), // Templated
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.f2d_drdy (f2d_drdy[1]), // Templated
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.gmii_tx_en (gmii_tx_en_1), // Templated
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.gmii_txd (gmii_txd_1[7:0]), // Templated
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.lnp_pnp (lnp_pnp[49:25]), // Templated
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.lnp_srdy (lnp_srdy[1]), // Templated
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.par_srdy (par_srdy[1]), // Templated
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.parr_drdy (parr_drdy[1]), // Templated
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.pbra_data (pbra_data_1[`PBR_SZ-1:0]), // Templated
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.pbra_srdy (pbra_srdy[1]), // Templated
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.pbrd_data (pbrd_data_1[`PBR_SZ-1:0]), // Templated
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.pbrd_srdy (pbrd_srdy[1]), // Templated
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.pbrr_drdy (pbrr_drdy[1]), // Templated
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.pm2f_data (pm2f_data_1[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
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.pm2f_srdy (pm2f_srdy[1]), // Templated
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.rlp_rd_page (rlp_rd_page[23:12]), // Templated
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.rlp_srdy (rlp_srdy[1]), // Templated
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.rlpr_drdy (rlpr_drdy[1]), // Templated
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// Inputs
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.clk (clk), // Templated
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.reset (reset), // Templated
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.drf_drdy (drf_drdy[1]), // Templated
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.f2d_data (f2d_data_1[`LL_PG_ASZ-1:0]), // Templated
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.f2d_srdy (f2d_srdy[1]), // Templated
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.gmii_rx_clk (gmii_rx_clk_1), // Templated
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.gmii_rx_dv (gmii_rx_dv_1), // Templated
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.gmii_rxd (gmii_rxd_1[7:0]), // Templated
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.lnp_drdy (lnp_drdy[1]), // Templated
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.par_drdy (par_drdy[1]), // Templated
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.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated
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.parr_srdy (parr_srdy[1]), // Templated
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.pbra_drdy (pbra_drdy[1]), // Templated
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.pbrd_drdy (pbrd_drdy[1]), // Templated
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.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated
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.pbrr_srdy (pbrr_srdy[1]), // Templated
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.pm2f_drdy (pm2f_drdy[1]), // Templated
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.rlp_drdy (rlp_drdy[1]), // Templated
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.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated
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.rlpr_srdy (rlpr_srdy[1])); // Templated
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port_macro #(2) p2
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(/*AUTOINST*/
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// Outputs
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.drf_page_list (drf_page_list[71:48]), // Templated
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.drf_srdy (drf_srdy[2]), // Templated
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.f2d_drdy (f2d_drdy[2]), // Templated
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.gmii_tx_en (gmii_tx_en_2), // Templated
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.gmii_txd (gmii_txd_2[7:0]), // Templated
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.lnp_pnp (lnp_pnp[74:50]), // Templated
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.lnp_srdy (lnp_srdy[2]), // Templated
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.par_srdy (par_srdy[2]), // Templated
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.parr_drdy (parr_drdy[2]), // Templated
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.pbra_data (pbra_data_2[`PBR_SZ-1:0]), // Templated
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.pbra_srdy (pbra_srdy[2]), // Templated
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.pbrd_data (pbrd_data_2[`PBR_SZ-1:0]), // Templated
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.pbrd_srdy (pbrd_srdy[2]), // Templated
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.pbrr_drdy (pbrr_drdy[2]), // Templated
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.pm2f_data (pm2f_data_2[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
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.pm2f_srdy (pm2f_srdy[2]), // Templated
|
239 |
|
|
.rlp_rd_page (rlp_rd_page[35:24]), // Templated
|
240 |
|
|
.rlp_srdy (rlp_srdy[2]), // Templated
|
241 |
|
|
.rlpr_drdy (rlpr_drdy[2]), // Templated
|
242 |
|
|
// Inputs
|
243 |
|
|
.clk (clk), // Templated
|
244 |
|
|
.reset (reset), // Templated
|
245 |
|
|
.drf_drdy (drf_drdy[2]), // Templated
|
246 |
|
|
.f2d_data (f2d_data_2[`LL_PG_ASZ-1:0]), // Templated
|
247 |
|
|
.f2d_srdy (f2d_srdy[2]), // Templated
|
248 |
|
|
.gmii_rx_clk (gmii_rx_clk_2), // Templated
|
249 |
|
|
.gmii_rx_dv (gmii_rx_dv_2), // Templated
|
250 |
|
|
.gmii_rxd (gmii_rxd_2[7:0]), // Templated
|
251 |
|
|
.lnp_drdy (lnp_drdy[2]), // Templated
|
252 |
|
|
.par_drdy (par_drdy[2]), // Templated
|
253 |
|
|
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated
|
254 |
|
|
.parr_srdy (parr_srdy[2]), // Templated
|
255 |
|
|
.pbra_drdy (pbra_drdy[2]), // Templated
|
256 |
|
|
.pbrd_drdy (pbrd_drdy[2]), // Templated
|
257 |
|
|
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated
|
258 |
|
|
.pbrr_srdy (pbrr_srdy[2]), // Templated
|
259 |
|
|
.pm2f_drdy (pm2f_drdy[2]), // Templated
|
260 |
|
|
.rlp_drdy (rlp_drdy[2]), // Templated
|
261 |
|
|
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated
|
262 |
|
|
.rlpr_srdy (rlpr_srdy[2])); // Templated
|
263 |
|
|
|
264 |
|
|
port_macro #(3) p3
|
265 |
|
|
(/*AUTOINST*/
|
266 |
|
|
// Outputs
|
267 |
|
|
.drf_page_list (drf_page_list[95:72]), // Templated
|
268 |
|
|
.drf_srdy (drf_srdy[3]), // Templated
|
269 |
|
|
.f2d_drdy (f2d_drdy[3]), // Templated
|
270 |
|
|
.gmii_tx_en (gmii_tx_en_3), // Templated
|
271 |
|
|
.gmii_txd (gmii_txd_3[7:0]), // Templated
|
272 |
|
|
.lnp_pnp (lnp_pnp[99:75]), // Templated
|
273 |
|
|
.lnp_srdy (lnp_srdy[3]), // Templated
|
274 |
|
|
.par_srdy (par_srdy[3]), // Templated
|
275 |
|
|
.parr_drdy (parr_drdy[3]), // Templated
|
276 |
|
|
.pbra_data (pbra_data_3[`PBR_SZ-1:0]), // Templated
|
277 |
|
|
.pbra_srdy (pbra_srdy[3]), // Templated
|
278 |
|
|
.pbrd_data (pbrd_data_3[`PBR_SZ-1:0]), // Templated
|
279 |
|
|
.pbrd_srdy (pbrd_srdy[3]), // Templated
|
280 |
|
|
.pbrr_drdy (pbrr_drdy[3]), // Templated
|
281 |
|
|
.pm2f_data (pm2f_data_3[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
|
282 |
|
|
.pm2f_srdy (pm2f_srdy[3]), // Templated
|
283 |
|
|
.rlp_rd_page (rlp_rd_page[47:36]), // Templated
|
284 |
|
|
.rlp_srdy (rlp_srdy[3]), // Templated
|
285 |
|
|
.rlpr_drdy (rlpr_drdy[3]), // Templated
|
286 |
|
|
// Inputs
|
287 |
|
|
.clk (clk), // Templated
|
288 |
|
|
.reset (reset), // Templated
|
289 |
|
|
.drf_drdy (drf_drdy[3]), // Templated
|
290 |
|
|
.f2d_data (f2d_data_3[`LL_PG_ASZ-1:0]), // Templated
|
291 |
|
|
.f2d_srdy (f2d_srdy[3]), // Templated
|
292 |
|
|
.gmii_rx_clk (gmii_rx_clk_3), // Templated
|
293 |
|
|
.gmii_rx_dv (gmii_rx_dv_3), // Templated
|
294 |
|
|
.gmii_rxd (gmii_rxd_3[7:0]), // Templated
|
295 |
|
|
.lnp_drdy (lnp_drdy[3]), // Templated
|
296 |
|
|
.par_drdy (par_drdy[3]), // Templated
|
297 |
|
|
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated
|
298 |
|
|
.parr_srdy (parr_srdy[3]), // Templated
|
299 |
|
|
.pbra_drdy (pbra_drdy[3]), // Templated
|
300 |
|
|
.pbrd_drdy (pbrd_drdy[3]), // Templated
|
301 |
|
|
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated
|
302 |
|
|
.pbrr_srdy (pbrr_srdy[3]), // Templated
|
303 |
|
|
.pm2f_drdy (pm2f_drdy[3]), // Templated
|
304 |
|
|
.rlp_drdy (rlp_drdy[3]), // Templated
|
305 |
|
|
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated
|
306 |
|
|
.rlpr_srdy (rlpr_srdy[3])); // Templated
|
307 |
|
|
|
308 |
|
|
control_pipe control0
|
309 |
|
|
(/*AUTOINST*/
|
310 |
|
|
// Outputs
|
311 |
|
|
.drf_drdy (drf_drdy[(`NUM_PORTS)-1:0]),
|
312 |
|
|
.f2d_data_0 (f2d_data_0[`LL_PG_ASZ-1:0]),
|
313 |
|
|
.f2d_data_1 (f2d_data_1[`LL_PG_ASZ-1:0]),
|
314 |
|
|
.f2d_data_2 (f2d_data_2[`LL_PG_ASZ-1:0]),
|
315 |
|
|
.f2d_data_3 (f2d_data_3[`LL_PG_ASZ-1:0]),
|
316 |
|
|
.f2d_srdy (f2d_srdy[3:0]),
|
317 |
|
|
.lnp_drdy (lnp_drdy[(`NUM_PORTS)-1:0]),
|
318 |
|
|
.par_drdy (par_drdy[(`NUM_PORTS)-1:0]),
|
319 |
|
|
.parr_page (parr_page[(`LL_PG_ASZ)-1:0]),
|
320 |
|
|
.parr_srdy (parr_srdy[(`NUM_PORTS)-1:0]),
|
321 |
|
|
.pm2f_drdy (pm2f_drdy[`NUM_PORTS-1:0]),
|
322 |
|
|
.rlp_drdy (rlp_drdy[(`NUM_PORTS)-1:0]),
|
323 |
|
|
.rlpr_data (rlpr_data[(`LL_PG_ASZ+1)-1:0]),
|
324 |
|
|
.rlpr_srdy (rlpr_srdy[(`NUM_PORTS)-1:0]),
|
325 |
|
|
// Inputs
|
326 |
|
|
.pm2f_data_0 (pm2f_data_0[`PM2F_SZ-1:0]),
|
327 |
|
|
.pm2f_data_1 (pm2f_data_1[`PM2F_SZ-1:0]),
|
328 |
|
|
.pm2f_data_2 (pm2f_data_2[`PM2F_SZ-1:0]),
|
329 |
|
|
.pm2f_data_3 (pm2f_data_3[`PM2F_SZ-1:0]),
|
330 |
|
|
.clk (clk),
|
331 |
|
|
.drf_page_list (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]),
|
332 |
|
|
.drf_srdy (drf_srdy[(`NUM_PORTS)-1:0]),
|
333 |
|
|
.f2d_drdy (f2d_drdy[3:0]),
|
334 |
|
|
.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]),
|
335 |
|
|
.lnp_srdy (lnp_srdy[(`NUM_PORTS)-1:0]),
|
336 |
|
|
.par_srdy (par_srdy[(`NUM_PORTS)-1:0]),
|
337 |
|
|
.parr_drdy (parr_drdy[(`NUM_PORTS)-1:0]),
|
338 |
|
|
.pm2f_srdy (pm2f_srdy[`NUM_PORTS-1:0]),
|
339 |
|
|
.reset (reset),
|
340 |
|
|
.rlp_rd_page (rlp_rd_page[(`NUM_PORTS)*(`LL_PG_ASZ)-1:0]),
|
341 |
|
|
.rlp_srdy (rlp_srdy[(`NUM_PORTS)-1:0]),
|
342 |
|
|
.rlpr_drdy (rlpr_drdy[(`NUM_PORTS)-1:0]));
|
343 |
|
|
|
344 |
|
|
packet_buffer pktbuf
|
345 |
|
|
(/*AUTOINST*/
|
346 |
|
|
// Outputs
|
347 |
|
|
.pbra_drdy (pbra_drdy[3:0]),
|
348 |
|
|
.pbrd_drdy (pbrd_drdy[3:0]),
|
349 |
|
|
.pbrr_srdy (pbrr_srdy[3:0]),
|
350 |
|
|
.pbrr_data (pbrr_data[`PFW_SZ-1:0]),
|
351 |
|
|
// Inputs
|
352 |
|
|
.clk (clk),
|
353 |
|
|
.reset (reset),
|
354 |
|
|
.pbra_srdy (pbra_srdy[3:0]),
|
355 |
|
|
.pbra_data_0 (pbra_data_0[`PBR_SZ-1:0]),
|
356 |
|
|
.pbra_data_1 (pbra_data_1[`PBR_SZ-1:0]),
|
357 |
|
|
.pbra_data_2 (pbra_data_2[`PBR_SZ-1:0]),
|
358 |
|
|
.pbra_data_3 (pbra_data_3[`PBR_SZ-1:0]),
|
359 |
|
|
.pbrd_data_0 (pbrd_data_0[`PBR_SZ-1:0]),
|
360 |
|
|
.pbrd_data_1 (pbrd_data_1[`PBR_SZ-1:0]),
|
361 |
|
|
.pbrd_data_2 (pbrd_data_2[`PBR_SZ-1:0]),
|
362 |
|
|
.pbrd_data_3 (pbrd_data_3[`PBR_SZ-1:0]),
|
363 |
|
|
.pbrd_srdy (pbrd_srdy[3:0]),
|
364 |
|
|
.pbrr_drdy (pbrr_drdy[3:0]));
|
365 |
|
|
|
366 |
|
|
endmodule // bridge_ex1
|
367 |
|
|
// Local Variables:
|
368 |
|
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
|
369 |
|
|
// End:
|