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ghutchis |
module port_macro
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ghutchis |
#(parameter port_num = 0,
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parameter lpsz = 12,
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parameter lpdsz = 13)
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ghutchis |
(input clk,
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input reset,
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input drf_drdy, // To dealloc of deallocator.v
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input [`LL_PG_ASZ-1:0] f2d_data, // To dealloc of deallocator.v
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input f2d_srdy, // To dealloc of deallocator.v
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input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
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input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
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input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
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input lnp_drdy, // To alloc of allocator.v
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input par_drdy, // To alloc of allocator.v
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input [`LL_PG_ASZ-1:0] parr_page, // To alloc of allocator.v
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input parr_srdy, // To alloc of allocator.v
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input pbra_drdy, // To alloc of allocator.v
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input pbrd_drdy, // To dealloc of deallocator.v
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input [`PFW_SZ-1:0] pbrr_data, // To dealloc of deallocator.v
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input pbrr_srdy, // To dealloc of deallocator.v
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input pm2f_drdy, // To pm2f_join of sd_ajoin2.v
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input rlp_drdy, // To dealloc of deallocator.v
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input [`LL_PG_ASZ:0] rlpr_data, // To dealloc of deallocator.v
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input rlpr_srdy, // To dealloc of deallocator.v
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ghutchis |
// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [`LL_PG_ASZ*2-1:0] drf_page_list, // From dealloc of deallocator.v
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output drf_srdy, // From dealloc of deallocator.v
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output f2d_drdy, // From dealloc of deallocator.v
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output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
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output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
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output [`LL_LNP_SZ-1:0] lnp_pnp, // From alloc of allocator.v
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output lnp_srdy, // From alloc of allocator.v
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output par_srdy, // From alloc of allocator.v
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output parr_drdy, // From alloc of allocator.v
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output [`PBR_SZ-1:0] pbra_data, // From alloc of allocator.v
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output pbra_srdy, // From alloc of allocator.v
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output [`PBR_SZ-1:0] pbrd_data, // From dealloc of deallocator.v
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output pbrd_srdy, // From dealloc of deallocator.v
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output pbrr_drdy, // From dealloc of deallocator.v
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output [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data,// From pm2f_join of sd_ajoin2.v
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output pm2f_srdy, // From pm2f_join of sd_ajoin2.v
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output [`LL_PG_ASZ-1:0] rlp_rd_page, // From dealloc of deallocator.v
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output rlp_srdy, // From dealloc of deallocator.v
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output rlpr_drdy // From dealloc of deallocator.v
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// End of automatics
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ghutchis |
);
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wire [`RX_USG_SZ-1:0] rx_usage;
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wire [`TX_USG_SZ-1:0] tx_usage;
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wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
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wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v
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wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v
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wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire a2f_drdy; // From pm2f_join of sd_ajoin2.v
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wire [`LL_PG_ASZ-1:0] a2f_end; // From alloc of allocator.v
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wire a2f_srdy; // From alloc of allocator.v
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wire [`LL_PG_ASZ-1:0] a2f_start; // From alloc of allocator.v
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wire crx_abort; // From con of concentrator.v
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wire crx_commit; // From con of concentrator.v
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wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
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wire crx_drdy; // From alloc of allocator.v
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wire crx_srdy; // From con of concentrator.v
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wire gmii_rx_reset; // From port_clocking of port_clocking.v
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wire [`PAR_DATA_SZ-1:0] p2f_data; // From pkt_parse of pkt_parse.v
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wire p2f_drdy; // From pm2f_join of sd_ajoin2.v
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wire p2f_srdy; // From pkt_parse of pkt_parse.v
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wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
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wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
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wire pdo_drdy; // From con of concentrator.v
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wire pdo_srdy; // From pkt_parse of pkt_parse.v
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wire ptx_drdy; // From dst of distributor.v
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wire ptx_srdy; // From dealloc of deallocator.v
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wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
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wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
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wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
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wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
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wire rxg_drdy; // From pkt_parse of pkt_parse.v
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wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
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wire [1:0] txg_code; // From dst of distributor.v
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wire [7:0] txg_data; // From dst of distributor.v
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wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
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wire txg_srdy; // From dst of distributor.v
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// End of automatics
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port_clocking port_clocking
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(/*AUTOINST*/
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// Outputs
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.gmii_rx_reset (gmii_rx_reset),
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// Inputs
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.clk (clk),
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.reset (reset),
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.gmii_rx_clk (gmii_rx_clk));
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/* sd_rx_gigmac AUTO_TEMPLATE
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(
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.clk (gmii_rx_clk),
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.reset (gmii_rx_reset),
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.rxg_\(.*\) (rxc_rxg_\1[]),
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);
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*/
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sd_rx_gigmac rx_gigmac
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(
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.cfg_check_crc (1'b0),
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/*AUTOINST*/
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// Outputs
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.rxg_srdy (rxc_rxg_srdy), // Templated
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.rxg_code (rxc_rxg_code[1:0]), // Templated
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.rxg_data (rxc_rxg_data[7:0]), // Templated
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// Inputs
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.clk (gmii_rx_clk), // Templated
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.reset (gmii_rx_reset), // Templated
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.gmii_rx_dv (gmii_rx_dv),
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.gmii_rxd (gmii_rxd[7:0]),
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.rxg_drdy (rxc_rxg_drdy)); // Templated
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/* sd_fifo_s AUTO_TEMPLATE
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(
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.c_clk (gmii_rx_clk),
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.c_reset (gmii_rx_reset),
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.c_data ({rxc_rxg_code,rxc_rxg_data}),
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.p_data ({rxg_code,rxg_data}),
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.p_clk (clk),
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.p_reset (reset),
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.c_\(.*\) (rxc_rxg_\1[]),
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.p_\(.*\) (rxg_\1[]),
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);
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*/
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sd_fifo_s #(8+2,16,1) rx_sync_fifo
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(/*AUTOINST*/
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// Outputs
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.c_drdy (rxc_rxg_drdy), // Templated
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.p_srdy (rxg_srdy), // Templated
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.p_data ({rxg_code,rxg_data}), // Templated
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// Inputs
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.c_clk (gmii_rx_clk), // Templated
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.c_reset (gmii_rx_reset), // Templated
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.c_srdy (rxc_rxg_srdy), // Templated
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.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
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.p_clk (clk), // Templated
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.p_reset (reset), // Templated
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.p_drdy (rxg_drdy)); // Templated
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pkt_parse #(port_num) pkt_parse
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(
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/*AUTOINST*/
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// Outputs
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.rxg_drdy (rxg_drdy),
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.p2f_srdy (p2f_srdy),
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.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
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.pdo_srdy (pdo_srdy),
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.pdo_code (pdo_code[1:0]),
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.pdo_data (pdo_data[7:0]),
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// Inputs
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31 |
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.clk (clk),
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.reset (reset),
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.rxg_srdy (rxg_srdy),
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.rxg_code (rxg_code[1:0]),
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.rxg_data (rxg_data[7:0]),
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.p2f_drdy (p2f_drdy),
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.pdo_drdy (pdo_drdy));
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ghutchis |
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/* concentrator AUTO_TEMPLATE
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(
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.c_\(.*\) (pdo_\1[]),
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.p_\(.*\) (crx_\1[]),
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);
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*/
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concentrator con
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(/*AUTOINST*/
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// Outputs
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.c_drdy (pdo_drdy), // Templated
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.p_data (crx_data[`PFW_SZ-1:0]), // Templated
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.p_srdy (crx_srdy), // Templated
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.p_commit (crx_commit), // Templated
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.p_abort (crx_abort), // Templated
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8 |
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// Inputs
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31 |
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.clk (clk),
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.reset (reset),
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.c_data (pdo_data[7:0]), // Templated
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.c_code (pdo_code[1:0]), // Templated
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.c_srdy (pdo_srdy), // Templated
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.p_drdy (crx_drdy)); // Templated
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8 |
ghutchis |
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31 |
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/* allocator AUTO_TEMPLATE
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(
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);
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*/
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allocator alloc
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199 |
8 |
ghutchis |
(/*AUTOINST*/
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// Outputs
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31 |
ghutchis |
.crx_drdy (crx_drdy),
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.par_srdy (par_srdy),
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.parr_drdy (parr_drdy),
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.lnp_srdy (lnp_srdy),
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.lnp_pnp (lnp_pnp[`LL_LNP_SZ-1:0]),
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.pbra_data (pbra_data[`PBR_SZ-1:0]),
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.pbra_srdy (pbra_srdy),
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.a2f_start (a2f_start[`LL_PG_ASZ-1:0]),
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.a2f_end (a2f_end[`LL_PG_ASZ-1:0]),
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.a2f_srdy (a2f_srdy),
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8 |
ghutchis |
// Inputs
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31 |
ghutchis |
.clk (clk),
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.reset (reset),
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.crx_abort (crx_abort),
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.crx_commit (crx_commit),
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.crx_data (crx_data[`PFW_SZ-1:0]),
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.crx_srdy (crx_srdy),
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.par_drdy (par_drdy),
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.parr_srdy (parr_srdy),
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220 |
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.parr_page (parr_page[`LL_PG_ASZ-1:0]),
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221 |
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.lnp_drdy (lnp_drdy),
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.pbra_drdy (pbra_drdy),
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.a2f_drdy (a2f_drdy));
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224 |
8 |
ghutchis |
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225 |
31 |
ghutchis |
/* sd_ajoin2 AUTO_TEMPLATE
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226 |
8 |
ghutchis |
(
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31 |
ghutchis |
.c2_data ({a2f_end,a2f_start}),
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228 |
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.c1_\(.*\) (p2f_\1[]),
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.c2_\(.*\) (a2f_\1[]),
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.p_\(.*\) (pm2f_\1[]),
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);
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232 |
8 |
ghutchis |
*/
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233 |
31 |
ghutchis |
sd_ajoin2 #(.c1_width(`PAR_DATA_SZ), .c2_width(`LL_PG_ASZ*2)) pm2f_join
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234 |
8 |
ghutchis |
(/*AUTOINST*/
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// Outputs
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236 |
31 |
ghutchis |
.c1_drdy (p2f_drdy), // Templated
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237 |
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.c2_drdy (a2f_drdy), // Templated
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.p_srdy (pm2f_srdy), // Templated
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.p_data (pm2f_data[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
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240 |
8 |
ghutchis |
// Inputs
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241 |
31 |
ghutchis |
.clk (clk),
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242 |
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.reset (reset),
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243 |
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.c1_srdy (p2f_srdy), // Templated
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244 |
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.c1_data (p2f_data[(`PAR_DATA_SZ)-1:0]), // Templated
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.c2_srdy (a2f_srdy), // Templated
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.c2_data ({a2f_end,a2f_start}), // Templated
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.p_drdy (pm2f_drdy)); // Templated
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248 |
8 |
ghutchis |
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249 |
31 |
ghutchis |
deallocator dealloc
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250 |
8 |
ghutchis |
(/*AUTOINST*/
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251 |
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// Outputs
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252 |
31 |
ghutchis |
.f2d_drdy (f2d_drdy),
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253 |
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.rlp_srdy (rlp_srdy),
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254 |
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.rlp_rd_page (rlp_rd_page[`LL_PG_ASZ-1:0]),
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255 |
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.rlpr_drdy (rlpr_drdy),
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.drf_srdy (drf_srdy),
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257 |
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.drf_page_list (drf_page_list[`LL_PG_ASZ*2-1:0]),
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.pbrd_data (pbrd_data[`PBR_SZ-1:0]),
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259 |
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.pbrd_srdy (pbrd_srdy),
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.pbrr_drdy (pbrr_drdy),
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.ptx_srdy (ptx_srdy),
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262 |
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.ptx_data (ptx_data[`PFW_SZ-1:0]),
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263 |
8 |
ghutchis |
// Inputs
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264 |
31 |
ghutchis |
.clk (clk),
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265 |
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.reset (reset),
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266 |
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.port_num (port_num[1:0]),
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267 |
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.f2d_srdy (f2d_srdy),
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.f2d_data (f2d_data[`LL_PG_ASZ-1:0]),
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269 |
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.rlp_drdy (rlp_drdy),
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270 |
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.rlpr_srdy (rlpr_srdy),
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271 |
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.rlpr_data (rlpr_data[`LL_PG_ASZ:0]),
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272 |
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.drf_drdy (drf_drdy),
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273 |
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.pbrd_drdy (pbrd_drdy),
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274 |
|
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.pbrr_srdy (pbrr_srdy),
|
275 |
|
|
.pbrr_data (pbrr_data[`PFW_SZ-1:0]),
|
276 |
|
|
.ptx_drdy (ptx_drdy));
|
277 |
8 |
ghutchis |
|
278 |
|
|
/* distributor AUTO_TEMPLATE
|
279 |
|
|
(
|
280 |
|
|
.p_\(.*\) (txg_\1[]),
|
281 |
|
|
);
|
282 |
|
|
*/
|
283 |
|
|
distributor dst
|
284 |
|
|
(/*AUTOINST*/
|
285 |
|
|
// Outputs
|
286 |
31 |
ghutchis |
.ptx_drdy (ptx_drdy),
|
287 |
|
|
.p_srdy (txg_srdy), // Templated
|
288 |
|
|
.p_code (txg_code[1:0]), // Templated
|
289 |
|
|
.p_data (txg_data[7:0]), // Templated
|
290 |
8 |
ghutchis |
// Inputs
|
291 |
31 |
ghutchis |
.clk (clk),
|
292 |
|
|
.reset (reset),
|
293 |
|
|
.ptx_srdy (ptx_srdy),
|
294 |
|
|
.ptx_data (ptx_data[`PFW_SZ-1:0]),
|
295 |
|
|
.p_drdy (txg_drdy)); // Templated
|
296 |
8 |
ghutchis |
|
297 |
|
|
sd_tx_gigmac tx_gmii
|
298 |
|
|
(/*AUTOINST*/
|
299 |
|
|
// Outputs
|
300 |
31 |
ghutchis |
.gmii_tx_en (gmii_tx_en),
|
301 |
|
|
.gmii_txd (gmii_txd[7:0]),
|
302 |
|
|
.txg_drdy (txg_drdy),
|
303 |
8 |
ghutchis |
// Inputs
|
304 |
31 |
ghutchis |
.clk (clk),
|
305 |
|
|
.reset (reset),
|
306 |
|
|
.txg_srdy (txg_srdy),
|
307 |
|
|
.txg_code (txg_code[1:0]),
|
308 |
|
|
.txg_data (txg_data[7:0]));
|
309 |
8 |
ghutchis |
|
310 |
|
|
endmodule // port_macro
|
311 |
|
|
// Local Variables:
|
312 |
|
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
|
313 |
|
|
// End:
|