OpenCores
URL https://opencores.org/ocsvn/tg68/tg68/trunk

Subversion Repositories tg68

[/] [tg68/] [trunk/] [VHDL/] [TG68_fast.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 tobiflex 
------------------------------------------------------------------------------
2 
------------------------------------------------------------------------------
3 
--                                                                          --
4 
-- This is the 68000 software compatible Kernal of TG68                     --
5 
--                                                                          --
6 
-- Copyright (c) 2007-2010 Tobias Gubener <tobiflex@opencores.org>          --
7 
--                                                                          --
8 
-- This source file is free software: you can redistribute it and/or modify --
9 
-- it under the terms of the GNU Lesser General Public License as published --
10 
-- by the Free Software Foundation, either version 3 of the License, or     --
11 
-- (at your option) any later version.                                      --
12 
--                                                                          --
13 
-- This source file is distributed in the hope that it will be useful,      --
14 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
15 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
16 
-- GNU General Public License for more details.                             --
17 
--                                                                          --
18 
-- You should have received a copy of the GNU General Public License        --
19 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
20 
--                                                                          --
21 
------------------------------------------------------------------------------
22 
------------------------------------------------------------------------------
23 
--
24 
-- Revision 1.08 2010/06/14
25 
-- Bugfix Movem with regmask==xFFFF
26 
-- Add missing Illegal $4AFC
27 
--
28 
-- Revision 1.07 2009/10/02
29 
-- Bugfix Movem with regmask==x0000
30 
--
31 
-- Revision 1.06 2009/02/10
32 
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
33 
-- Example lsr.l D2,D2
34 
-- Thanks to Peter Graf for report
35 
--
36 
-- Revision 1.05 2009/01/26
37 
-- Implement missing RTR
38 
-- Thanks to Peter Graf for report
39 
--
40 
-- Revision 1.04 2007/12/29
41 
-- size improvement
42 
-- change signal "microaddr" to one hot state machine
43 
--
44 
-- Revision 1.03 2007/12/21
45 
-- Thanks to Andreas Ehliar
46 
-- Split regfile to use blockram for registers
47 
-- insert "WHEN OTHERS => null;" on END CASE;
48 
--
49 
-- Revision 1.02 2007/12/17
50 
-- Bugfix jsr  nn.w
51 
--
52 
-- Revision 1.01 2007/11/28
53 
-- add MOVEP
54 
-- Bugfix Interrupt in MOVEQ
55 
--
56 
-- Revision 1.0 2007/11/05
57 
-- Clean up code and first release
58 
--
59 
-- known bugs/todo:
60 
-- Add CHK INSTRUCTION
61 
-- full decode ILLEGAL INSTRUCTIONS
62 
-- Add FC Output
63 
-- add odd Address test
64 
-- add TRACE
65 
 
66 
 
67 
library ieee;
68 
use ieee.std_logic_1164.all;
69 
use ieee.std_logic_unsigned.all;
70 
 
71 
entity TG68_fast is
72 
   port(clk               : in std_logic;
73 
        reset             : in std_logic;                       --low active
74 
        clkena_in         : in std_logic:='1';
75 
        data_in           : in std_logic_vector(15 downto 0);
76 
                IPL                               : in std_logic_vector(2 downto 0):="111";
77 
        test_IPL          : in std_logic:='0';           --only for debugging
78 
        address           : out std_logic_vector(31 downto 0);
79 
        data_write        : out std_logic_vector(15 downto 0);
80 
        state_out         : out std_logic_vector(1 downto 0);
81 
                LDS, UDS                  : out std_logic;
82 
        decodeOPC         : buffer std_logic;
83 
                wr                                : out std_logic
84 
                );
85 
end TG68_fast;
86 
 
87 
architecture logic of TG68_fast is
88 
 
89 
   signal state           : std_logic_vector(1 downto 0);
90 
   signal clkena              : std_logic;
91 
   signal TG68_PC         : std_logic_vector(31 downto 0);
92 
   signal TG68_PC_add     : std_logic_vector(31 downto 0);
93 
   signal memaddr         : std_logic_vector(31 downto 0);
94 
   signal memaddr_in      : std_logic_vector(31 downto 0);
95 
   signal ea_data         : std_logic_vector(31 downto 0);
96 
   signal ea_data_OP1     : std_logic;
97 
   signal setaddrlong     : std_logic;
98 
   signal OP1out, OP2out  : std_logic_vector(31 downto 0);
99 
   signal OP1outbrief     : std_logic_vector(15 downto 0);
100 
   signal OP1in           : std_logic_vector(31 downto 0);
101 
   signal data_write_tmp  : std_logic_vector(31 downto 0);
102 
   signal Xtmp            : std_logic_vector(31 downto 0);
103 
   signal PC_dataa, PC_datab, PC_result  : std_logic_vector(31 downto 0);
104 
   signal setregstore     : std_logic;
105 
   signal datatype        : std_logic_vector(1 downto 0);
106 
   signal longread            : std_logic;
107 
   signal longreaddirect  : std_logic;
108 
   signal long_done           : std_logic;
109 
   signal nextpass            : std_logic;
110 
   signal setnextpass     : std_logic;
111 
   signal setdispbyte     : std_logic;
112 
   signal setdisp             : std_logic;
113 
   signal setdispbrief    : std_logic;
114 
   signal regdirectsource : std_logic;
115 
   signal endOPC              : std_logic;
116 
   signal postadd             : std_logic;
117 
   signal presub              : std_logic;
118 
   signal addsub_a        : std_logic_vector(31 downto 0);
119 
   signal addsub_b        : std_logic_vector(31 downto 0);
120 
   signal addsub_q        : std_logic_vector(31 downto 0);
121 
   signal briefext        : std_logic_vector(31 downto 0);
122 
   signal setbriefext     : std_logic;
123 
   signal addsub              : std_logic;
124 
   signal c_in            : std_logic_vector(3 downto 0);
125 
   signal c_out           : std_logic_vector(2 downto 0);
126 
   signal add_result      : std_logic_vector(33 downto 0);
127 
   signal addsub_ofl      : std_logic_vector(2 downto 0);
128 
   signal flag_z          : std_logic_vector(2 downto 0);
129 
 
130 
   signal last_data_read  : std_logic_vector(15 downto 0);
131 
   signal data_read       : std_logic_vector(31 downto 0);
132 
 
133 
   signal registerin      : std_logic_vector(31 downto 0);
134 
   signal reg_QA          : std_logic_vector(31 downto 0);
135 
   signal reg_QB          : std_logic_vector(31 downto 0);
136 
   signal Hwrena,Lwrena   : std_logic;
137 
   signal Regwrena            : std_logic;
138 
   signal rf_dest_addr    : std_logic_vector(6 downto 0);
139 
   signal rf_source_addr  : std_logic_vector(6 downto 0);
140 
   signal rf_dest_addr_tmp              : std_logic_vector(6 downto 0);
141 
   signal rf_source_addr_tmp    : std_logic_vector(6 downto 0);
142 
   signal opcode                  : std_logic_vector(15 downto 0);
143 
   signal laststate               : std_logic_vector(1 downto 0);
144 
   signal setstate            : std_logic_vector(1 downto 0);
145 
 
146 
   signal mem_address     : std_logic_vector(31 downto 0);
147 
   signal memaddr_a       : std_logic_vector(31 downto 0);
148 
   signal mem_data_read   : std_logic_vector(31 downto 0);
149 
   signal mem_data_write  : std_logic_vector(31 downto 0);
150 
        signal set_mem_rega   : std_logic;
151 
   signal data_read_ram   : std_logic_vector(31 downto 0);
152 
   signal data_read_uart  : std_logic_vector(7 downto 0);
153 
 
154 
   signal counter_reg     : std_logic_vector(31 downto 0);
155 
 
156 
        signal TG68_PC_br8    : std_logic;
157 
        signal TG68_PC_brw    : std_logic;
158 
        signal TG68_PC_nop    : std_logic;
159 
        signal setgetbrief    : std_logic;
160 
        signal getbrief       : std_logic;
161 
        signal brief          : std_logic_vector(15 downto 0);
162 
        signal dest_areg      : std_logic;
163 
        signal source_areg    : std_logic;
164 
        signal data_is_source : std_logic;
165 
        signal set_store_in_tmp    : std_logic;
166 
        signal store_in_tmp   : std_logic;
167 
        signal write_back     : std_logic;
168 
        signal setaddsub      : std_logic;
169 
        signal setstackaddr   : std_logic;
170 
        signal writePC        : std_logic;
171 
        signal writePC_add    : std_logic;
172 
        signal set_TG68_PC_dec: std_logic;
173 
        signal TG68_PC_dec    : std_logic_vector(1 downto 0);
174 
        signal directPC       : std_logic;
175 
        signal set_directPC   : std_logic;
176 
        signal execOPC        : std_logic;
177 
        signal fetchOPC       : std_logic;
178 
        signal Flags          : std_logic_vector(15 downto 0);   --T.S..III ...XNZVC
179 
        signal set_Flags      : std_logic_vector(3 downto 0);    --NZVC
180 
        signal exec_ADD       : std_logic;
181 
        signal exec_OR        : std_logic;
182 
        signal exec_AND       : std_logic;
183 
        signal exec_EOR       : std_logic;
184 
        signal exec_MOVE      : std_logic;
185 
        signal exec_MOVEQ     : std_logic;
186 
        signal exec_MOVESR    : std_logic;
187 
        signal exec_DIRECT    : std_logic;
188 
        signal exec_ADDQ      : std_logic;
189 
        signal exec_CMP       : std_logic;
190 
        signal exec_ROT       : std_logic;
191 
        signal exec_exg       : std_logic;
192 
        signal exec_swap      : std_logic;
193 
        signal exec_write_back: std_logic;
194 
        signal exec_tas       : std_logic;
195 
        signal exec_EXT       : std_logic;
196 
        signal exec_ABCD      : std_logic;
197 
        signal exec_SBCD      : std_logic;
198 
        signal exec_MULU      : std_logic;
199 
        signal exec_DIVU      : std_logic;
200 
    signal exec_Scc       : std_logic;
201 
    signal exec_CPMAW     : std_logic;
202 
        signal set_exec_ADD   : std_logic;
203 
        signal set_exec_OR    : std_logic;
204 
        signal set_exec_AND   : std_logic;
205 
        signal set_exec_EOR   : std_logic;
206 
        signal set_exec_MOVE  : std_logic;
207 
        signal set_exec_MOVEQ : std_logic;
208 
        signal set_exec_MOVESR: std_logic;
209 
        signal set_exec_ADDQ  : std_logic;
210 
        signal set_exec_CMP   : std_logic;
211 
        signal set_exec_ROT   : std_logic;
212 
        signal set_exec_tas   : std_logic;
213 
        signal set_exec_EXT   : std_logic;
214 
        signal set_exec_ABCD  : std_logic;
215 
        signal set_exec_SBCD  : std_logic;
216 
        signal set_exec_MULU  : std_logic;
217 
        signal set_exec_DIVU  : std_logic;
218 
    signal set_exec_Scc   : std_logic;
219 
    signal set_exec_CPMAW : std_logic;
220 
 
221 
        signal condition      : std_logic;
222 
        signal OP2out_one     : std_logic;
223 
        signal OP1out_zero    : std_logic;
224 
        signal ea_to_pc       : std_logic;
225 
        signal ea_build       : std_logic;
226 
        signal ea_only        : std_logic;
227 
        signal get_ea_now     : std_logic;
228 
        signal source_lowbits : std_logic;
229 
        signal dest_hbits     : std_logic;
230 
        signal rot_rot        : std_logic;
231 
        signal rot_lsb        : std_logic;
232 
        signal rot_msb        : std_logic;
233 
        signal rot_XC         : std_logic;
234 
        signal set_rot_nop    : std_logic;
235 
        signal rot_nop        : std_logic;
236 
    signal rot_out        : std_logic_vector(31 downto 0);
237 
    signal rot_bits       : std_logic_vector(1 downto 0);
238 
    signal rot_cnt        : std_logic_vector(5 downto 0);
239 
    signal set_rot_cnt    : std_logic_vector(5 downto 0);
240 
        signal movem_busy     : std_logic;
241 
        signal set_movem_busy : std_logic;
242 
        signal movem_addr     : std_logic;
243 
        signal movem_regaddr  : std_logic_vector(3 downto 0);
244 
        signal movem_mask     : std_logic_vector(15 downto 0);
245 
        signal set_get_movem_mask  : std_logic;
246 
        signal get_movem_mask : std_logic;
247 
        signal maskzero       : std_logic;
248 
        signal test_maskzero  : std_logic;
249 
        signal movem_muxa     : std_logic_vector(7 downto 0);
250 
        signal movem_muxb     : std_logic_vector(3 downto 0);
251 
        signal movem_muxc     : std_logic_vector(1 downto 0);
252 
    signal movem_presub   : std_logic;
253 
    signal save_memaddr   : std_logic;
254 
    signal movem_bits     : std_logic_vector(4 downto 0);
255 
    signal ea_calc_b      : std_logic_vector(31 downto 0);
256 
    signal set_mem_addsub : std_logic;
257 
    signal bit_bits       : std_logic_vector(1 downto 0);
258 
    signal bit_number_reg : std_logic_vector(4 downto 0);
259 
    signal bit_number     : std_logic_vector(4 downto 0);
260 
    signal exec_Bits      : std_logic;
261 
    signal bits_out       : std_logic_vector(31 downto 0);
262 
    signal one_bit_in     : std_logic;
263 
    signal one_bit_out    : std_logic;
264 
        signal set_get_bitnumber        : std_logic;
265 
        signal get_bitnumber  : std_logic;
266 
        signal mem_byte           : std_logic;
267 
        signal wait_mem_byte  : std_logic;
268 
        signal movepl             : std_logic;
269 
        signal movepw             : std_logic;
270 
        signal set_movepl         : std_logic;
271 
        signal set_movepw         : std_logic;
272 
        signal set_direct_data: std_logic;
273 
        signal use_direct_data: std_logic;
274 
        signal direct_data        : std_logic;
275 
        signal set_get_extendedOPC      : std_logic;
276 
        signal get_extendedOPC: std_logic;
277 
    signal setstate_delay : std_logic_vector(1 downto 0);
278 
    signal setstate_mux   : std_logic_vector(1 downto 0);
279 
    signal use_XZFlag     : std_logic;
280 
    signal use_XFlag      : std_logic;
281 
 
282 
    signal dummy_a                : std_logic_vector(8 downto 0);
283 
    signal niba_l                 : std_logic_vector(5 downto 0);
284 
    signal niba_h                 : std_logic_vector(5 downto 0);
285 
    signal niba_lc                : std_logic;
286 
    signal niba_hc                : std_logic;
287 
    signal bcda_lc                : std_logic;
288 
    signal bcda_hc                : std_logic;
289 
    signal dummy_s                : std_logic_vector(8 downto 0);
290 
    signal nibs_l                 : std_logic_vector(5 downto 0);
291 
    signal nibs_h                 : std_logic_vector(5 downto 0);
292 
    signal nibs_lc                : std_logic;
293 
    signal nibs_hc                : std_logic;
294 
    signal dummy_mulu     : std_logic_vector(31 downto 0);
295 
    signal dummy_div      : std_logic_vector(31 downto 0);
296 
    signal dummy_div_sub  : std_logic_vector(16 downto 0);
297 
    signal dummy_div_over : std_logic_vector(16 downto 0);
298 
    signal set_V_Flag     : std_logic;
299 
    signal OP1sign                : std_logic;
300 
    signal set_sign               : std_logic;
301 
    signal sign                   : std_logic;
302 
    signal sign2                  : std_logic;
303 
    signal muls_msb               : std_logic;
304 
    signal mulu_reg       : std_logic_vector(31 downto 0);
305 
    signal div_reg        : std_logic_vector(31 downto 0);
306 
    signal div_sign               : std_logic;
307 
    signal div_quot       : std_logic_vector(31 downto 0);
308 
    signal div_ovl            : std_logic;
309 
    signal pre_V_Flag     : std_logic;
310 
    signal set_vectoraddr : std_logic;
311 
    signal writeSR            : std_logic;
312 
        signal trap_illegal   : std_logic;
313 
        signal trap_priv      : std_logic;
314 
        signal trap_1010      : std_logic;
315 
        signal trap_1111      : std_logic;
316 
        signal trap_trap      : std_logic;
317 
        signal trap_trapv     : std_logic;
318 
        signal trap_interrupt : std_logic;
319 
        signal trapmake       : std_logic;
320 
        signal trapd          : std_logic;
321 
--   signal trap_PC        : std_logic_vector(31 downto 0);
322 
    signal trap_SR        : std_logic_vector(15 downto 0);
323 
 
324 
    signal set_directSR   : std_logic;
325 
    signal directSR           : std_logic;
326 
    signal set_directCCR  : std_logic;
327 
    signal directCCR      : std_logic;
328 
    signal set_stop           : std_logic;
329 
    signal stop           : std_logic;
330 
    signal trap_vector    : std_logic_vector(31 downto 0);
331 
    signal to_USP             : std_logic;
332 
    signal from_USP           : std_logic;
333 
    signal to_SR              : std_logic;
334 
    signal from_SR            : std_logic;
335 
    signal illegal_write_mode   : std_logic;
336 
    signal illegal_read_mode    : std_logic;
337 
    signal illegal_byteaddr         : std_logic;
338 
    signal use_SP             : std_logic;
339 
 
340 
    signal no_Flags           : std_logic;
341 
        signal IPL_nr             : std_logic_vector(2 downto 0);
342 
        signal rIPL_nr            : std_logic_vector(2 downto 0);
343 
    signal interrupt      : std_logic;
344 
    signal SVmode             : std_logic;
345 
        signal trap_chk   : std_logic;
346 
        signal test_delay         : std_logic_vector(2 downto 0);
347 
        signal set_PCmarker       : std_logic;
348 
        signal PCmarker       : std_logic;
349 
        signal set_Z_error        : std_logic;
350 
        signal Z_error        : std_logic;
351 
 
352 
        type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
353 
                                                  st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
354 
                                                  movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
355 
                                                  movep1, movep2, movep3, movep4, movep5, init1, init2,
356 
                                                  mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
357 
                                                  div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
358 
        signal micro_state              : micro_states;
359 
        signal next_micro_state         : micro_states;
360 
 
361 
        type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
362 
        signal regfile_low        : regfile_t;
363 
        signal regfile_high       : regfile_t;
364 
        signal RWindex_A          : integer range 0 to 16;
365 
        signal RWindex_B          : integer range 0 to 16;
366 
 
367 
 
368 
BEGIN
369 
 
370 
-----------------------------------------------------------------------------
371 
-- Registerfile
372 
-----------------------------------------------------------------------------
373 
 
374 
        RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
375 
        RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
376 
 
377 
        PROCESS (clk)
378 
        BEGIN
379 
                IF falling_edge(clk) THEN
380 
                    IF clkena='1' THEN
381 
                                reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
382 
                                reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
383 
                        END IF;
384 
                END IF;
385 
                IF rising_edge(clk) THEN
386 
                    IF clkena='1' THEN
387 
                                IF Lwrena='1' THEN
388 
                                        regfile_low(RWindex_A) <= registerin(15 downto 0);
389 
                                END IF;
390 
                                IF Hwrena='1' THEN
391 
                                        regfile_high(RWindex_A) <= registerin(31 downto 16);
392 
                                END IF;
393 
                        END IF;
394 
                END IF;
395 
        END PROCESS;
396 
 
397 
 
398 
 
399 
        address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
400 
        LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
401 
        UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
402 
        state_out <= state;
403 
        wr <= '0' WHEN state="11" ELSE '1';
404 
        IPL_nr <= NOT IPL;
405 
 
406 
 
407 
-----------------------------------------------------------------------------
408 
-- "ALU"
409 
-----------------------------------------------------------------------------
410 
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
411 
        BEGIN
412 
                IF addsub='1' THEN              --ADD
413 
                        add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
414 
                ELSE                                    --SUB
415 
                        add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
416 
                END IF;
417 
                addsub_q <= add_result(32 downto 1);
418 
                c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
419 
                c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
420 
                c_in(3) <= add_result(33);
421 
                addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7));    --V Byte
422 
                addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15));        --V Word
423 
                addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31));        --V Long
424 
                c_out <= c_in(3 downto 1);
425 
END PROCESS;
426 
 
427 
-----------------------------------------------------------------------------
428 
-- MEM_IO
429 
-----------------------------------------------------------------------------
430 
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
431 
         movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
432 
         set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
433 
         data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
434 
        BEGIN
435 
                clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
436 
 
437 
                IF rising_edge(clk) THEN
438 
                        IF clkena='1' THEN
439 
                                trap_vector(31 downto 8) <= (others => '0');
440 
                --              IF trap_addr_fault='1' THEN
441 
                --                      trap_vector(7 downto 0) <= X"08";
442 
                --              END IF;
443 
                --              IF trap_addr_error='1' THEN
444 
                --                      trap_vector(7 downto 0) <= X"0C";
445 
                --              END IF;
446 
                                IF trap_illegal='1' THEN
447 
                                        trap_vector(7 downto 0) <= X"10";
448 
                                END IF;
449 
                                IF z_error='1' THEN
450 
                                        trap_vector(7 downto 0) <= X"14";
451 
                                END IF;
452 
--                              IF trap_chk='1' THEN
453 
--                                      trap_vector(7 downto 0) <= X"18";
454 
--                              END IF;
455 
                                IF trap_trapv='1' THEN
456 
                                        trap_vector(7 downto 0) <= X"1C";
457 
                                END IF;
458 
                                IF trap_priv='1' THEN
459 
                                        trap_vector(7 downto 0) <= X"20";
460 
                                END IF;
461 
                --              IF trap_trace='1' THEN
462 
                --                      trap_vector(7 downto 0) <= X"24";
463 
                --              END IF;
464 
                                IF trap_1010='1' THEN
465 
                                        trap_vector(7 downto 0) <= X"28";
466 
                                END IF;
467 
                                IF trap_1111='1' THEN
468 
                                        trap_vector(7 downto 0) <= X"2C";
469 
                                END IF;
470 
                                IF trap_trap='1' THEN
471 
                                        trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
472 
                                END IF;
473 
                                IF interrupt='1' THEN
474 
                                        trap_vector(7 downto 2) <= "011"&rIPL_nr;
475 
                                END IF;
476 
                        END IF;
477 
                END IF;
478 
 
479 
                memaddr_a(3 downto 0) <= "0000";
480 
                memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
481 
                memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
482 
                memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
483 
                IF movem_presub='1' THEN
484 
                        IF movem_busy='1' OR longread='1' THEN
485 
                                memaddr_a(3 downto 0) <= "1110";
486 
                        END IF;
487 
                ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
488 
                        memaddr_a(1) <= '1';
489 
                ELSIF execOPC='1' THEN
490 
                        IF datatype="10" THEN
491 
                                memaddr_a(3 downto 0) <= "1100";
492 
                        ELSE
493 
                                memaddr_a(3 downto 0) <= "1110";
494 
                        END IF;
495 
                ELSIF setdisp='1' THEN
496 
                        IF setdispbrief='1' THEN
497 
                                memaddr_a <= briefext;
498 
                        ELSIF setdispbyte='1' THEN
499 
                                memaddr_a(7 downto 0) <= brief(7 downto 0);
500 
                        ELSE
501 
                                memaddr_a(15 downto 0) <= brief;
502 
                        END IF;
503 
                END IF;
504 
 
505 
                memaddr_in <= memaddr+memaddr_a;
506 
                IF longread='0' THEN
507 
                        IF set_mem_addsub='1' THEN
508 
                                memaddr_in <= addsub_q;
509 
                        ELSIF set_vectoraddr='1' THEN
510 
                                memaddr_in <= trap_vector;
511 
                        ELSIF interrupt='1' THEN
512 
                                memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
513 
                        ELSIF set_mem_rega='1' THEN
514 
                                memaddr_in <= reg_QA;
515 
                        ELSIF setaddrlong='1' AND longread='0' THEN
516 
                                memaddr_in <= data_read;
517 
                        ELSIF decodeOPC='1' THEN
518 
                                memaddr_in <= TG68_PC;
519 
                        END IF;
520 
                END IF;
521 
 
522 
                data_read(15 downto 0) <= data_in;
523 
                data_read(31 downto 16) <= (OTHERS=>data_in(15));
524 
                IF long_done='1' THEN
525 
                        data_read(31 downto 16) <= last_data_read;
526 
                END IF;
527 
                IF mem_byte='1' AND memaddr(0)='0' THEN
528 
                        data_read(7 downto 0) <= data_in(15 downto 8);
529 
                END IF;
530 
 
531 
                IF longread='1' THEN
532 
                        data_write <= data_write_tmp(31 downto 16);
533 
                ELSE
534 
                        data_write(7 downto 0) <= data_write_tmp(7 downto 0);
535 
                        IF mem_byte='1' THEN
536 
                                data_write(15 downto 8) <= data_write_tmp(7 downto 0);
537 
                        ELSE
538 
                                data_write(15 downto 8) <= data_write_tmp(15 downto 8);
539 
                                IF datatype="00" THEN
540 
                                        data_write(7 downto 0) <= data_write_tmp(15 downto 8);
541 
                                END IF;
542 
                        END IF;
543 
                END IF;
544 
 
545 
                IF reset='0' THEN
546 
                        longread <= '0';
547 
                        long_done <= '0';
548 
                ELSIF rising_edge(clk) THEN
549 
                IF clkena_in='1' THEN
550 
                                last_data_read <= data_in;
551 
                                        long_done <= longread;
552 
                                IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
553 
                                                memaddr <= memaddr_in;
554 
                                END IF;
555 
                                IF get_extendedOPC='0' THEN
556 
 
557 
                                        IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
558 
                                                longread <= '1';
559 
                                        ELSE
560 
                                                longread <= '0';
561 
                                        END IF;
562 
                                END IF;
563 
 
564 
                        END IF;
565 
                END IF;
566 
    END PROCESS;
567 
-----------------------------------------------------------------------------
568 
-- brief
569 
-----------------------------------------------------------------------------
570 
process (clk, brief, OP1out)
571 
        begin
572 
                IF brief(11)='1' THEN
573 
                        OP1outbrief <= OP1out(31 downto 16);
574 
                ELSE
575 
                        OP1outbrief <= (OTHERS=>OP1out(15));
576 
                END IF;
577 
                IF rising_edge(clk) THEN
578 
                IF clkena='1' THEN
579 
                                briefext <= OP1outbrief&OP1out(15 downto 0);
580 
--                              CASE brief(10 downto 9) IS
581 
--                                      WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
582 
--                                      WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
583 
--                                      WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
584 
--                                      WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
585 
--                              END CASE;
586 
                end if;
587 
        end if;
588 
   end process;
589 
 
590 
-----------------------------------------------------------------------------
591 
-- PC Calc + fetch opcode
592 
-----------------------------------------------------------------------------
593 
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
594 
                 setstate_delay, setstate)
595 
        begin
596 
                PC_dataa <= TG68_PC;
597 
                PC_datab(2 downto 0) <= "010";
598 
                PC_datab(7 downto 3) <= (others => PC_datab(2));
599 
                PC_datab(15 downto 8) <= (others => PC_datab(7));
600 
                PC_datab(31 downto 16) <= (others => PC_datab(15));
601 
                IF execOPC='0' THEN
602 
                        IF TG68_PC_br8='1' THEN
603 
                                PC_datab(7 downto 0) <= opcode(7 downto 0);
604 
                        END IF;
605 
                        IF TG68_PC_dec(1)='1' THEN
606 
                                PC_datab(2) <= '1';
607 
                        END IF;
608 
                        IF TG68_PC_brw = '1' THEN
609 
                                PC_datab(15 downto 0) <= last_data_read(15 downto 0);
610 
                        END IF;
611 
                END IF;
612 
                TG68_PC_add <= PC_dataa+PC_datab;
613 
 
614 
                IF get_extendedOPC='1' THEN
615 
                        setstate_mux <= setstate_delay;
616 
                ELSE
617 
                        setstate_mux <= setstate;
618 
                END IF;
619 
 
620 
 
621 
        IF reset = '0' THEN
622 
                        opcode(15 downto 12) <= X"7";           --moveq
623 
                        opcode(8 downto 6) <= "010";            --long
624 
                        TG68_PC <= (others =>'0');
625 
                        state <= "01";
626 
                        decodeOPC <= '0';
627 
                        fetchOPC <= '0';
628 
                        endOPC <= '0';
629 
                        interrupt <= '0';
630 
                        trap_interrupt <= '1';
631 
                        execOPC <= '0';
632 
                        getbrief <= '0';
633 
                        TG68_PC_dec <= "00";
634 
                        directPC <= '0';
635 
                        directSR <= '0';
636 
                        directCCR <= '0';
637 
                        stop <= '0';
638 
                        exec_ADD <= '0';
639 
                        exec_OR <= '0';
640 
                        exec_AND <= '0';
641 
                        exec_EOR <= '0';
642 
                        exec_MOVE <= '0';
643 
                        exec_MOVEQ <= '0';
644 
                        exec_MOVESR <= '0';
645 
                        exec_ADDQ <= '0';
646 
                        exec_CMP <= '0';
647 
                        exec_ROT <= '0';
648 
                        exec_EXT <= '0';
649 
                        exec_ABCD <= '0';
650 
                        exec_SBCD <= '0';
651 
                        exec_MULU <= '0';
652 
                        exec_DIVU <= '0';
653 
                        exec_Scc <= '0';
654 
                        exec_CPMAW <= '0';
655 
                        mem_byte <= '0';
656 
                        rot_cnt <="000001";
657 
                        rot_nop <= '0';
658 
                        get_extendedOPC <= '0';
659 
                        get_bitnumber <= '0';
660 
                        get_movem_mask <= '0';
661 
                        test_maskzero <= '0';
662 
                        movepl <= '0';
663 
                        movepw <= '0';
664 
                        test_delay <= "000";
665 
                        PCmarker <= '0';
666 
                ELSIF rising_edge(clk) THEN
667 
                IF clkena_in='1' THEN
668 
                                get_extendedOPC <= set_get_extendedOPC;
669 
                                get_bitnumber <= set_get_bitnumber;
670 
                                get_movem_mask <= set_get_movem_mask;
671 
                                test_maskzero <= get_movem_mask;
672 
                                setstate_delay <= setstate;
673 
 
674 
                                TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
675 
                                IF directPC='1' AND clkena='1' THEN
676 
                                        TG68_PC <= data_read;
677 
                                ELSIF ea_to_pc='1' AND longread='0' THEN
678 
                                        TG68_PC <= memaddr_in;
679 
                                ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
680 
                                        TG68_PC <= TG68_PC_add;
681 
                                END IF;
682 
 
683 
                                IF get_bitnumber='1' THEN
684 
                                        bit_number_reg <= data_read(4 downto 0);
685 
                                END IF;
686 
 
687 
                        IF clkena='1' OR get_extendedOPC='1' THEN
688 
                                        IF set_get_extendedOPC='1' THEN
689 
                                                state <= "00";
690 
                                        ELSIF get_extendedOPC='1' THEN
691 
                                                state <= setstate_mux;
692 
                                        ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
693 
                                                state <= "01";          --decode cycle, execute cycle
694 
                                        ELSE
695 
                                                state <= setstate_mux;
696 
                                        END IF;
697 
                                        IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
698 
                                                mem_byte <= '1';
699 
                                        ELSE
700 
                                                mem_byte <= '0';
701 
                                        END IF;
702 
 
703 
                                END IF;
704 
                        END IF;
705 
 
706 
                IF clkena='1' THEN
707 
                                exec_ADD <= '0';
708 
                                exec_OR <= '0';
709 
                                exec_AND <= '0';
710 
                                exec_EOR <= '0';
711 
                                exec_MOVE <= '0';
712 
                                exec_MOVEQ <= '0';
713 
                                exec_MOVESR <= '0';
714 
                                exec_ADDQ <= '0';
715 
                                exec_CMP <= '0';
716 
                                exec_ROT <= '0';
717 
                                exec_ABCD <= '0';
718 
                                exec_SBCD <= '0';
719 
                                fetchOPC <= '0';
720 
                                exec_CPMAW <= '0';
721 
                                endOPC <= '0';
722 
                                interrupt <= '0';
723 
                                execOPC <= '0';
724 
                                exec_EXT <= '0';
725 
                                exec_Scc <= '0';
726 
                                rot_nop <= '0';
727 
                                decodeOPC <= fetchOPC;
728 
                                directPC <= set_directPC;
729 
                                directSR <= set_directSR;
730 
                                directCCR <= set_directCCR;
731 
                                exec_MULU <= set_exec_MULU;
732 
                                exec_DIVU <= set_exec_DIVU;
733 
                                movepl <= '0';
734 
                                movepw <= '0';
735 
 
736 
                                stop <= set_stop OR (stop AND NOT interrupt);
737 
                                IF      set_PCmarker='1' THEN
738 
                                        PCmarker <= '1';
739 
                                ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
740 
                                        PCmarker <= '0';
741 
                                END IF;
742 
                                IF (decodeOPC OR execOPC)='1' THEN
743 
                                        rot_cnt <= set_rot_cnt;
744 
                                END IF;
745 
                                IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
746 
                                        nextpass <= '0';
747 
                                        IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
748 
                                                endOPC <= '1';
749 
                                                IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
750 
                                                        interrupt <= '1';
751 
                                                        rIPL_nr <= IPL_nr;
752 
                                                ELSE
753 
                                                        IF stop='0' THEN
754 
                                                                fetchOPC <= '1';
755 
                                                        END IF;
756 
                                                END IF;
757 
                                        END IF;
758 
                                        IF exec_write_back='0' OR state/="11" THEN
759 
                                                IF stop='0' THEN
760 
                                                        execOPC <= '1';
761 
                                                END IF;
762 
                                                exec_ADD <= set_exec_ADD;
763 
                                                exec_OR <= set_exec_OR;
764 
                                                exec_AND <= set_exec_AND;
765 
                                                exec_EOR <= set_exec_EOR;
766 
                                                exec_MOVE <= set_exec_MOVE;
767 
                                                exec_MOVEQ <= set_exec_MOVEQ;
768 
                                                exec_MOVESR <= set_exec_MOVESR;
769 
                                                exec_ADDQ <= set_exec_ADDQ;
770 
                                                exec_CMP <= set_exec_CMP;
771 
                                                exec_ROT <= set_exec_ROT;
772 
                                                exec_tas <= set_exec_tas;
773 
                                                exec_EXT <= set_exec_EXT;
774 
                                                exec_ABCD <= set_exec_ABCD;
775 
                                                exec_SBCD <= set_exec_SBCD;
776 
                                                exec_Scc <= set_exec_Scc;
777 
                                                exec_CPMAW <= set_exec_CPMAW;
778 
                                                rot_nop <= set_rot_nop;
779 
 
780 
                                        END IF;
781 
                                ELSE
782 
                                        IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
783 
                                                nextpass <= '1';
784 
                                        END IF;
785 
                                END IF;
786 
                                IF interrupt='1' THEN
787 
                                        opcode(15 downto 12) <= X"7";           --moveq
788 
                                        opcode(8 downto 6) <= "010";            --long
789 
--                                      trap_PC <= TG68_PC;
790 
                                        trap_interrupt <= '1';
791 
                                END IF;
792 
                                IF fetchOPC='1' THEN
793 
                                        trap_interrupt <= '0';
794 
                                        IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
795 
--                                      IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN  --nur für Validator
796 
                                                opcode <= X"60FE";
797 
                                                IF to_SR='0' THEN
798 
                                                        test_delay <= "001";
799 
                                                END IF;
800 
                                        ELSE
801 
                                                opcode <= data_read(15 downto 0);
802 
                                        END IF;
803 
                                        getbrief <= '0';
804 
--                                      trap_PC <= TG68_PC;
805 
                                ELSE
806 
                                        test_delay <= test_delay(1 downto 0)&'0';
807 
                                        getbrief <= setgetbrief;
808 
                                        movepl <= set_movepl;
809 
                                        movepw <= set_movepw;
810 
                                END IF;
811 
                                IF decodeOPC='1' OR interrupt='1' THEN
812 
                                        trap_SR <= Flags;
813 
                                END IF;
814 
 
815 
                                IF getbrief='1' THEN
816 
                                        brief <= data_read(15 downto 0);
817 
                                END IF;
818 
                end if;
819 
        end if;
820 
   end process;
821 
 
822 
-----------------------------------------------------------------------------
823 
-- handle EA_data, data_write_tmp
824 
-----------------------------------------------------------------------------
825 
PROCESS (clk, reset, opcode)
826 
        BEGIN
827 
        IF reset = '0' THEN
828 
                        set_store_in_tmp <='0';
829 
                        exec_DIRECT <= '0';
830 
                        exec_write_back <= '0';
831 
                        direct_data <= '0';
832 
                        use_direct_data <= '0';
833 
                        Z_error <= '0';
834 
                ELSIF rising_edge(clk) THEN
835 
                        IF clkena='1' THEN
836 
                                direct_data <= '0';
837 
                                IF endOPC='1' THEN
838 
                                        set_store_in_tmp <='0';
839 
                                        exec_DIRECT <= '0';
840 
                                        exec_write_back <= '0';
841 
                                        use_direct_data <= '0';
842 
                                        Z_error <= '0';
843 
                                ELSE
844 
                                        IF set_Z_error='1'  THEN
845 
                                                Z_error <= '1';
846 
                                        END IF;
847 
                                        exec_DIRECT <= set_exec_MOVE;
848 
                                        IF setstate_mux="10" AND write_back='1' THEN
849 
                                                exec_write_back <= '1';
850 
                                        END IF;
851 
                                END IF;
852 
                                IF set_direct_data='1' THEN
853 
                                        direct_data <= '1';
854 
                                        use_direct_data <= '1';
855 
                                END IF;
856 
                                IF set_exec_MOVE='1' AND state="11" THEN
857 
                                        use_direct_data <= '1';
858 
                                END IF;
859 
 
860 
                                IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
861 
                                        set_store_in_tmp <= '1';
862 
                                        ea_data <= data_read;
863 
                                END IF;
864 
 
865 
                                IF writePC_add='1' THEN
866 
                                        data_write_tmp <= TG68_PC_add;
867 
                                ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN            --fetchOPC für Trap
868 
                                        data_write_tmp <= TG68_PC;
869 
                                ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN              --get_ea_now='1' AND ea_only='1' ist für pea
870 
                                        data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)&registerin(6 downto 0);
871 
                                ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
872 
                                        data_write_tmp <= data_read;
873 
                                        IF  movepl='1' THEN
874 
                                                data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
875 
                                        END IF;
876 
                                ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
877 
                                        data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
878 
                                ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
879 
                                        data_write_tmp <= OP2out;
880 
                                ELSIF writeSR='1'THEN
881 
                                        data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
882 
                                END IF;
883 
                        END IF;
884 
                END IF;
885 
        END PROCESS;
886 
 
887 
-----------------------------------------------------------------------------
888 
-- set dest regaddr
889 
-----------------------------------------------------------------------------
890 
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
891 
        BEGIN
892 
                rf_dest_addr <= rf_dest_addr_tmp;
893 
                IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
894 
                        rf_dest_addr(4) <= Flags(13) OR trapmake;
895 
                END IF;
896 
                IF movem_addr='1' THEN
897 
                        IF movem_presub='1' THEN
898 
                                rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
899 
                        ELSE
900 
                                rf_dest_addr_tmp <= "000"&movem_regaddr;
901 
                        END IF;
902 
                ELSIF setbriefext='1' THEN
903 
                        rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
904 
                ELSIF setstackaddr='1' THEN
905 
                        rf_dest_addr_tmp <= "0001111";
906 
                ELSIF dest_hbits='1' THEN
907 
                        rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
908 
                ELSE
909 
                        IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
910 
                                rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
911 
                        ELSE
912 
                                rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
913 
                        END IF;
914 
                END IF;
915 
        END PROCESS;
916 
 
917 
-----------------------------------------------------------------------------
918 
-- set OP1
919 
-----------------------------------------------------------------------------
920 
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
921 
        BEGIN
922 
                OP1out <= reg_QA;
923 
                IF OP1out_zero='1' THEN
924 
                        OP1out <= (OTHERS => '0');
925 
                ELSIF from_SR='1' THEN
926 
                        OP1out(15 downto 0) <= Flags;
927 
                ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
928 
                        OP1out <= ea_data;
929 
                END IF;
930 
        END PROCESS;
931 
 
932 
-----------------------------------------------------------------------------
933 
-- set source regaddr
934 
-----------------------------------------------------------------------------
935 
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
936 
        BEGIN
937 
                rf_source_addr <= rf_source_addr_tmp;
938 
                IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
939 
                        rf_source_addr(4) <= Flags(13);
940 
                END IF;
941 
                IF movem_addr='1' THEN
942 
                        IF movem_presub='1' THEN
943 
                                rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
944 
                        ELSE
945 
                                rf_source_addr_tmp <= "000"&movem_regaddr;
946 
                        END IF;
947 
                ELSIF from_USP='1' THEN
948 
                        rf_source_addr_tmp <= "0001111";
949 
                ELSIF source_lowbits='1' THEN
950 
                        rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
951 
                ELSE
952 
                        rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
953 
                END IF;
954 
        END PROCESS;
955 
 
956 
-----------------------------------------------------------------------------
957 
-- set OP2
958 
-----------------------------------------------------------------------------
959 
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
960 
             ea_data_OP1, set_store_in_tmp, ea_data, movepl)
961 
        BEGIN
962 
                OP2out(15 downto 0) <= reg_QB(15 downto 0);
963 
                OP2out(31 downto 16) <= (OTHERS => OP2out(15));
964 
                IF OP2out_one='1' THEN
965 
                        OP2out(15 downto 0) <= "1111111111111111";
966 
                ELSIF exec_EXT='1' THEN
967 
                        IF opcode(6)='0' THEN    --ext.w
968 
                                OP2out(15 downto 8) <= (OTHERS => OP2out(7));
969 
                        END IF;
970 
                ELSIF use_direct_data='1' THEN
971 
                        OP2out <= data_write_tmp;
972 
                ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
973 
                        OP2out <= ea_data;
974 
                ELSIF exec_MOVEQ='1' THEN
975 
                        OP2out(7 downto 0) <= opcode(7 downto 0);
976 
                        OP2out(15 downto 8) <= (OTHERS => opcode(7));
977 
                ELSIF exec_ADDQ='1' THEN
978 
                        OP2out(2 downto 0) <= opcode(11 downto 9);
979 
                        IF opcode(11 downto 9)="000" THEN
980 
                                OP2out(3) <='1';
981 
                        ELSE
982 
                                OP2out(3) <='0';
983 
                        END IF;
984 
                        OP2out(15 downto 4) <= (OTHERS => '0');
985 
                ELSIF datatype="10" OR movepl='1' THEN
986 
                        OP2out(31 downto 16) <= reg_QB(31 downto 16);
987 
                END IF;
988 
        END PROCESS;
989 
 
990 
-----------------------------------------------------------------------------
991 
-- addsub
992 
-----------------------------------------------------------------------------
993 
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
994 
        BEGIN
995 
                addsub_a <= OP1out;
996 
                addsub_b <= OP2out;
997 
                addsub <= NOT presub;
998 
                c_in(0) <='0';
999 
                IF execOPC='0' AND OP2out_one='0' THEN
1000 
                        IF datatype="00" AND use_SP='0' THEN
1001 
                                addsub_b <= "00000000000000000000000000000001";
1002 
                        ELSIF datatype="10" AND (presub OR postadd)='1' THEN
1003 
                                addsub_b <= "00000000000000000000000000000100";
1004 
                        ELSE
1005 
                                addsub_b <= "00000000000000000000000000000010";
1006 
                        END IF;
1007 
                ELSE
1008 
                        IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
1009 
                                c_in(0) <= '1';
1010 
                        END IF;
1011 
                        addsub <= setaddsub;
1012 
                END IF;
1013 
    END PROCESS;
1014 
 
1015 
-----------------------------------------------------------------------------
1016 
-- Write Reg
1017 
-----------------------------------------------------------------------------
1018 
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
1019 
        BEGIN
1020 
                Lwrena <= '0';
1021 
                Hwrena <= '0';
1022 
                registerin <= OP1in;
1023 
 
1024 
                IF (presub='1' OR postadd='1') AND endOPC='0' THEN               -- -(An)+
1025 
                        Hwrena <= '1';
1026 
                        Lwrena <= '1';
1027 
                ELSIF Regwrena='1' AND maskzero='0' THEN         --read (mem)
1028 
                        Lwrena <= '1';
1029 
                        CASE datatype IS
1030 
                                WHEN "00" =>            --BYTE
1031 
                                        registerin(15 downto 8) <= reg_QA(15 downto 8);
1032 
                                WHEN "01" =>            --WORD
1033 
                                        IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
1034 
                                                Hwrena <='1';
1035 
                                        END IF;
1036 
                                WHEN OTHERS =>          --LONG
1037 
                                        Hwrena <= '1';
1038 
                        END CASE;
1039 
                END IF;
1040 
        END PROCESS;
1041 
 
1042 
------------------------------------------------------------------------------
1043 
--ALU
1044 
------------------------------------------------------------------------------
1045 
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
1046 
        dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
1047 
        exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
1048 
        memaddr_in, ea_only, get_ea_now)
1049 
        BEGIN
1050 
 
1051 
--BCD_ARITH-------------------------------------------------------------------
1052 
                --ADC
1053 
                        dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
1054 
                        niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
1055 
                        niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
1056 
 
1057 
                        niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
1058 
                        niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
1059 
                --SBC
1060 
                        dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
1061 
                        nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
1062 
                        nibs_lc <= nibs_l(5);
1063 
 
1064 
                        nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
1065 
                        nibs_hc <= nibs_h(5);
1066 
------------------------------------------------------------------------------
1067 
 
1068 
                        flag_z <= "000";
1069 
 
1070 
                        OP1in <= addsub_q;
1071 
                        IF movem_addr='1' THEN
1072 
                                OP1in <= data_read;
1073 
                        ELSIF exec_ABCD='1' THEN
1074 
                                OP1in(7 downto 0) <= dummy_a(7 downto 0);
1075 
                        ELSIF exec_SBCD='1' THEN
1076 
                                OP1in(7 downto 0) <= dummy_s(7 downto 0);
1077 
                        ELSIF exec_MULU='1' THEN
1078 
                                OP1in <= dummy_mulu;
1079 
                        ELSIF exec_DIVU='1' AND execOPC='1' THEN
1080 
                                OP1in <= dummy_div;
1081 
                        ELSIF exec_OR='1' THEN
1082 
                                OP1in <= OP2out OR OP1out;
1083 
                        ELSIF exec_AND='1' OR exec_Scc='1' THEN
1084 
                                OP1in <= OP2out AND OP1out;
1085 
                        ELSIF exec_EOR='1' THEN
1086 
                                OP1in <= OP2out XOR OP1out;
1087 
                        ELSIF exec_MOVE='1' OR exec_exg='1' THEN
1088 
                                OP1in <= OP2out;
1089 
                        ELSIF exec_ROT='1' THEN
1090 
                                OP1in <= rot_out;
1091 
                        ELSIF save_memaddr='1' THEN
1092 
                                OP1in <= memaddr;
1093 
                        ELSIF get_ea_now='1' AND ea_only='1' THEN
1094 
                                OP1in <= memaddr_in;
1095 
                        ELSIF exec_swap='1' THEN
1096 
                                OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
1097 
                        ELSIF exec_bits='1' THEN
1098 
                                OP1in <= bits_out;
1099 
                        ELSIF exec_MOVESR='1' THEN
1100 
                                OP1in(15 downto 0) <= Flags;
1101 
                        END IF;
1102 
 
1103 
                        IF use_XZFlag='1' AND flags(2)='0' THEN
1104 
                                flag_z <= "000";
1105 
                        ELSIF OP1in(7 downto 0)="00000000" THEN
1106 
                                flag_z(0) <= '1';
1107 
                                IF OP1in(15 downto 8)="00000000" THEN
1108 
                                        flag_z(1) <= '1';
1109 
                                        IF OP1in(31 downto 16)="0000000000000000" THEN
1110 
                                                flag_z(2) <= '1';
1111 
                                        END IF;
1112 
                                END IF;
1113 
                        END IF;
1114 
 
1115 
--                                      --Flags NZVC
1116 
                        IF datatype="00" THEN                                           --Byte
1117 
                                set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
1118 
                                IF exec_ABCD='1' THEN
1119 
                                        set_flags(0) <= dummy_a(8);
1120 
                                ELSIF exec_SBCD='1' THEN
1121 
                                        set_flags(0) <= dummy_s(8);
1122 
                                END IF;
1123 
                        ELSIF datatype="10" OR exec_CPMAW='1' THEN                                              --Long
1124 
                                set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
1125 
                        ELSE                                            --Word
1126 
                                set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
1127 
                        END IF;
1128 
        END PROCESS;
1129 
 
1130 
------------------------------------------------------------------------------
1131 
--Flags
1132 
------------------------------------------------------------------------------
1133 
PROCESS (clk, reset, opcode)
1134 
        BEGIN
1135 
                IF reset='0' THEN
1136 
                        Flags(13) <= '1';
1137 
                        SVmode <= '1';
1138 
                        Flags(10 downto 8) <= "111";
1139 
                ELSIF rising_edge(clk) THEN
1140 
 
1141 
                IF clkena = '1' THEN
1142 
                                IF directSR='1' THEN
1143 
                                        Flags <= data_read(15 downto 0);
1144 
                                END IF;
1145 
                                IF directCCR='1' THEN
1146 
                                        Flags(7 downto 0) <= data_read(7 downto 0);
1147 
                                END IF;
1148 
                                IF interrupt='1' THEN
1149 
                                        Flags(10 downto 8) <=rIPL_nr;
1150 
                                        SVmode <= '1';
1151 
                                END IF;
1152 
                                IF writeSR='1' OR interrupt='1' THEN
1153 
                                        Flags(13) <='1';
1154 
                                END IF;
1155 
                                IF endOPC='1' AND to_SR='0' THEN
1156 
                                        SVmode <= Flags(13);
1157 
                                END IF;
1158 
                                IF execOPC='1' AND to_SR='1' THEN
1159 
                                        Flags(7 downto 0) <= OP1in(7 downto 0);                   --CCR
1160 
                                        IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN              --move to CCR wird als word gespeichert
1161 
                                                Flags(15 downto 8) <= OP1in(15 downto 8);       --SR
1162 
                                                SVmode <= OP1in(13);
1163 
                                        END IF;
1164 
                                ELSIF Z_error='1' THEN
1165 
                                        IF opcode(8)='0' THEN
1166 
                                                Flags(3 downto 0) <= "1000";
1167 
                                        ELSE
1168 
                                                Flags(3 downto 0) <= "0100";
1169 
                                        END IF;
1170 
                                ELSIF no_Flags='0' AND trapmake='0' THEN
1171 
                                        IF exec_ADD='1' THEN
1172 
                                                Flags(4) <= set_flags(0);
1173 
                                        ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
1174 
                                                Flags(4) <= rot_XC;
1175 
                                        END IF;
1176 
 
1177 
                                        IF (exec_ADD OR exec_CMP)='1' THEN
1178 
                                                Flags(3 downto 0) <= set_flags;
1179 
                                        ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
1180 
                                                Flags(1) <= '0';
1181 
                                        ELSIF exec_DIVU='1' THEN
1182 
                                                IF set_V_Flag='1' THEN
1183 
                                                        Flags(3 downto 0) <= "1010";
1184 
                                                ELSE
1185 
                                                        Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
1186 
                                                END IF;
1187 
                                        ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
1188 
                                                Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
1189 
                                        ELSIF exec_ROT='1' THEN
1190 
                                                Flags(3 downto 2) <= set_flags(3 downto 2);
1191 
                                                Flags(0) <= rot_XC;
1192 
                                                IF rot_bits="00" THEN           --ASL/ASR
1193 
                                                        Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
1194 
                                                END IF;
1195 
                                        ELSIF exec_bits='1' THEN
1196 
                                                Flags(2) <= NOT one_bit_in;
1197 
                                        END IF;
1198 
                                END IF;
1199 
                        END IF;
1200 
                END IF;
1201 
        END PROCESS;
1202 
 
1203 
-----------------------------------------------------------------------------
1204 
-- execute opcode
1205 
-----------------------------------------------------------------------------
1206 
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
1207 
             Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
1208 
             Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
1209 
        BEGIN
1210 
                TG68_PC_br8 <= '0';
1211 
                TG68_PC_brw <= '0';
1212 
                TG68_PC_nop <= '0';
1213 
                setstate <= "00";
1214 
                Regwrena <= '0';
1215 
                postadd <= '0';
1216 
                presub <= '0';
1217 
                movem_presub <= '0';
1218 
                setaddsub <= '1';
1219 
                setaddrlong <= '0';
1220 
                setnextpass <= '0';
1221 
                regdirectsource <= '0';
1222 
                setdisp <= '0';
1223 
                setdispbyte <= '0';
1224 
                setdispbrief <= '0';
1225 
                setbriefext <= '0';
1226 
                setgetbrief <= '0';
1227 
                longreaddirect <= '0';
1228 
                dest_areg <= '0';
1229 
                source_areg <= '0';
1230 
                data_is_source <= '0';
1231 
                write_back <= '0';
1232 
                setstackaddr <= '0';
1233 
                writePC <= '0';
1234 
                writePC_add <= '0';
1235 
                set_TG68_PC_dec <= '0';
1236 
                set_directPC <= '0';
1237 
                set_exec_ADD <= '0';
1238 
                set_exec_OR <= '0';
1239 
                set_exec_AND <= '0';
1240 
                set_exec_EOR <= '0';
1241 
                set_exec_MOVE <= '0';
1242 
                set_exec_MOVEQ <= '0';
1243 
                set_exec_MOVESR <= '0';
1244 
                set_exec_ADDQ <= '0';
1245 
                set_exec_CMP <= '0';
1246 
                set_exec_ROT <= '0';
1247 
                set_exec_EXT <= '0';
1248 
                set_exec_CPMAW <= '0';
1249 
                OP2out_one <= '0';
1250 
                ea_to_pc <= '0';
1251 
                ea_build <= '0';
1252 
                get_ea_now <= '0';
1253 
                rot_bits <= "XX";
1254 
                set_rot_nop <= '0';
1255 
                set_rot_cnt <= "000001";
1256 
                set_movem_busy <= '0';
1257 
                set_get_movem_mask <= '0';
1258 
                save_memaddr <= '0';
1259 
                set_mem_addsub <= '0';
1260 
                exec_exg <= '0';
1261 
                exec_swap <= '0';
1262 
                exec_Bits <= '0';
1263 
                set_get_bitnumber <= '0';
1264 
                dest_hbits <= '0';
1265 
                source_lowbits <= '0';
1266 
                set_mem_rega <= '0';
1267 
                ea_data_OP1 <= '0';
1268 
                ea_only <= '0';
1269 
                set_direct_data <= '0';
1270 
                set_get_extendedOPC <= '0';
1271 
                set_exec_tas <= '0';
1272 
                OP1out_zero <= '0';
1273 
                use_XZFlag <= '0';
1274 
                use_XFlag <= '0';
1275 
                set_exec_ABCD <= '0';
1276 
                set_exec_SBCD <= '0';
1277 
                set_exec_MULU <= '0';
1278 
                set_exec_DIVU <= '0';
1279 
                set_exec_Scc <= '0';
1280 
                trap_illegal <='0';
1281 
                trap_priv <='0';
1282 
                trap_1010 <='0';
1283 
                trap_1111 <='0';
1284 
                trap_trap <='0';
1285 
                trap_trapv <= '0';
1286 
                trapmake <='0';
1287 
                set_vectoraddr <='0';
1288 
                writeSR <= '0';
1289 
                set_directSR <= '0';
1290 
                set_directCCR <= '0';
1291 
                set_stop <= '0';
1292 
                from_SR <= '0';
1293 
                to_SR <= '0';
1294 
                from_USP <= '0';
1295 
                to_USP <= '0';
1296 
                illegal_write_mode <= '0';
1297 
                illegal_read_mode <= '0';
1298 
                illegal_byteaddr <= '0';
1299 
                no_Flags <= '0';
1300 
                set_PCmarker <= '0';
1301 
                use_SP <= '0';
1302 
                set_Z_error <= '0';
1303 
                wait_mem_byte <= '0';
1304 
                set_movepl <= '0';
1305 
                set_movepw <= '0';
1306 
 
1307 
                trap_chk <= '0';
1308 
                next_micro_state <= idle;
1309 
 
1310 
------------------------------------------------------------------------------
1311 
--Sourcepass
1312 
------------------------------------------------------------------------------
1313 
                IF ea_only='0' AND get_ea_now='1' THEN
1314 
                        setstate <= "10";
1315 
                END IF;
1316 
 
1317 
                IF ea_build='1' THEN
1318 
                        CASE opcode(5 downto 3) IS              --source
1319 
                                WHEN "010"|"011"|"100" =>                                               -- -(An)+
1320 
                                        get_ea_now <='1';
1321 
                                        setnextpass <= '1';
1322 
                                        IF opcode(4)='1' THEN
1323 
                                                set_mem_rega <= '1';
1324 
                                        ELSE
1325 
                                                set_mem_addsub <= '1';
1326 
                                        END IF;
1327 
                                        IF opcode(3)='1' THEN   --(An)+
1328 
                                                postadd <= '1';
1329 
                                                IF opcode(2 downto 0)="111" THEN
1330 
                                                        use_SP <= '1';
1331 
                                                END IF;
1332 
                                        END IF;
1333 
                                        IF opcode(5)='1' THEN   -- -(An)
1334 
                                                presub <= '1';
1335 
                                                IF opcode(2 downto 0)="111" THEN
1336 
                                                        use_SP <= '1';
1337 
                                                END IF;
1338 
                                        END IF;
1339 
                                        IF opcode(4 downto 3)/="10" THEN
1340 
                                                regwrena <= '1';
1341 
                                        END IF;
1342 
                                WHEN "101" =>                           --(d16,An)
1343 
                                        next_micro_state <= ld_dAn1;
1344 
                                        setgetbrief <='1';
1345 
                                        set_mem_regA <= '1';
1346 
                                WHEN "110" =>                           --(d8,An,Xn)
1347 
                                        next_micro_state <= ld_AnXn1;
1348 
                                        setgetbrief <='1';
1349 
                                        set_mem_regA <= '1';
1350 
                                WHEN "111" =>
1351 
                                        CASE opcode(2 downto 0) IS
1352 
                                                WHEN "000" =>                           --(xxxx).w
1353 
                                                        next_micro_state <= ld_nn;
1354 
                                                WHEN "001" =>                           --(xxxx).l
1355 
                                                        longreaddirect <= '1';
1356 
                                                        next_micro_state <= ld_nn;
1357 
                                                WHEN "010" =>                           --(d16,PC)
1358 
                                                        next_micro_state <= ld_dAn1;
1359 
                                                        setgetbrief <= '1';
1360 
                                                        set_PCmarker <= '1';
1361 
                                                WHEN "011" =>                           --(d8,PC,Xn)
1362 
                                                        next_micro_state <= ld_AnXn1;
1363 
                                                        setgetbrief <= '1';
1364 
                                                        set_PCmarker <= '1';
1365 
                                                WHEN "100" =>                           --#data
1366 
                                                        setnextpass <= '1';
1367 
                                                        set_direct_data <= '1';
1368 
                                                        IF datatype="10" THEN
1369 
                                                                longreaddirect <= '1';
1370 
                                                        END IF;
1371 
                                                WHEN OTHERS =>
1372 
                                        END CASE;
1373 
                                WHEN OTHERS =>
1374 
                        END CASE;
1375 
                END IF;
1376 
------------------------------------------------------------------------------
1377 
--prepere opcode
1378 
------------------------------------------------------------------------------
1379 
                CASE opcode(7 downto 6) IS
1380 
                        WHEN "00" => datatype <= "00";          --Byte
1381 
                        WHEN "01" => datatype <= "01";          --Word
1382 
                        WHEN OTHERS => datatype <= "10";        --Long
1383 
                END CASE;
1384 
 
1385 
                IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
1386 
                        setstate <="11";
1387 
                END IF;
1388 
 
1389 
------------------------------------------------------------------------------
1390 
--test illegal mode
1391 
------------------------------------------------------------------------------
1392 
                IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
1393 
                        illegal_write_mode <= '1';
1394 
                END IF;
1395 
                IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
1396 
                        illegal_read_mode <= '1';
1397 
                END IF;
1398 
                IF opcode(5 downto 3)="001" AND datatype="00" THEN
1399 
                        illegal_byteaddr <= '1';
1400 
                END IF;
1401 
 
1402 
 
1403 
                CASE opcode(15 downto 12) IS
1404 
-- 0000 ----------------------------------------------------------------------------
1405 
                        WHEN "0000" =>
1406 
                        IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
1407 
                                datatype <= "00";                               --Byte
1408 
                                use_SP <= '1';
1409 
                                no_Flags <='1';
1410 
                                IF opcode(7)='0' THEN
1411 
                                        set_exec_move <= '1';
1412 
                                        set_movepl <= '1';
1413 
                                END IF;
1414 
                                IF decodeOPC='1' THEN
1415 
                                        IF opcode(7)='0' THEN
1416 
                                                set_direct_data <= '1';
1417 
                                        END IF;
1418 
                                        next_micro_state <= movep1;
1419 
                                        setgetbrief <='1';
1420 
                                        set_mem_regA <= '1';
1421 
                                END IF;
1422 
                                IF opcode(7)='0' AND endOPC='1' THEN
1423 
                                        IF opcode(6)='1' THEN
1424 
                                                datatype <= "10";               --Long
1425 
                                        ELSE
1426 
                                                datatype <= "01";               --Word
1427 
                                        END IF;
1428 
                                        dest_hbits <='1';
1429 
                                        regwrena <= '1';
1430 
                                END IF;
1431 
                        ELSE
1432 
                                IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN                             --Bits
1433 
                                        IF execOPC='1' AND get_extendedOPC='0' THEN
1434 
                                                IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
1435 
                                                        regwrena <= '1';
1436 
                                                END IF;
1437 
                                                exec_Bits <= '1';
1438 
                                                ea_data_OP1 <= '1';
1439 
                                        END IF;
1440 
--                                      IF get_extendedOPC='1' THEN
1441 
--                                              datatype <= "01";                       --Word
1442 
--                                      ELS
1443 
                                        IF opcode(5 downto 4)="00" THEN
1444 
                                                datatype <= "10";                       --Long
1445 
                                        ELSE
1446 
                                                datatype <= "00";                       --Byte
1447 
                                                IF opcode(7 downto 6)/="00" THEN
1448 
                                                        write_back <= '1';
1449 
                                                END IF;
1450 
                                        END IF;
1451 
                                        IF decodeOPC='1' THEN
1452 
                                                ea_build <= '1';
1453 
                                                IF opcode(8)='0' THEN
1454 
                                                        IF opcode(5 downto 4)/="00" THEN        --Dn, An
1455 
                                                                set_get_extendedOPC <= '1';
1456 
                                                        END IF;
1457 
                                                        set_get_bitnumber <= '1';
1458 
                                                END IF;
1459 
                                        END IF;
1460 
                                ELSE                                                            --andi, ...xxxi
1461 
                                        IF opcode(11 downto 8)="0000" THEN      --ORI
1462 
                                                set_exec_OR <= '1';
1463 
                                        END IF;
1464 
                                        IF opcode(11 downto 8)="0010" THEN      --ANDI
1465 
                                                set_exec_AND <= '1';
1466 
                                        END IF;
1467 
                                        IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN        --SUBI, ADDI
1468 
                                                set_exec_ADD <= '1';
1469 
                                        END IF;
1470 
                                        IF opcode(11 downto 8)="1010" THEN      --EORI
1471 
                                                set_exec_EOR <= '1';
1472 
                                        END IF;
1473 
                                        IF opcode(11 downto 8)="1100" THEN      --CMPI
1474 
                                                set_exec_CMP <= '1';
1475 
                                        ELSIF trapmake='0' THEN
1476 
                                                write_back <= '1';
1477 
                                        END IF;
1478 
                                        IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN               --SR
1479 
--                                      IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN              --SR
1480 
                                                IF SVmode='0' AND opcode(6)='1' THEN  --SR
1481 
                                                        trap_priv <= '1';
1482 
                                                        trapmake <= '1';
1483 
                                                ELSE
1484 
                                                        from_SR <= '1';
1485 
                                                        to_SR <= '1';
1486 
                                                        IF decodeOPC='1' THEN
1487 
                                                                setnextpass <= '1';
1488 
                                                                set_direct_data <= '1';
1489 
                                                        END IF;
1490 
                                                END IF;
1491 
                                        ELSE
1492 
                                                IF decodeOPC='1' THEN
1493 
                                                        IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100"       --ANDI, ORI, SUBI
1494 
                                                           OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN       --ADDI, EORI, CMPI
1495 
        --                                              IF (set_exec_AND OR set_exec_OR OR set_exec_ADD         --ANDI, ORI, SUBI
1496 
        --                                                 OR set_exec_EOR OR set_exec_CMP)='1' THEN    --ADDI, EORI, CMPI
1497 
 
1498 
                                                                next_micro_state <= andi;
1499 
                                                                set_direct_data <= '1';
1500 
                                                                IF datatype="10" THEN
1501 
                                                                        longreaddirect <= '1';
1502 
                                                                END IF;
1503 
                                                        END IF;
1504 
                                                END IF;
1505 
 
1506 
                                                IF execOPC='1' THEN
1507 
                                                        ea_data_OP1 <= '1';
1508 
                                                        IF opcode(11 downto 8)/="1100" THEN     --CMPI
1509 
                                                                IF endOPC='1' THEN
1510 
                                                                        Regwrena <= '1';
1511 
                                                                END IF;
1512 
                                                        END IF;
1513 
                                                        IF opcode(11 downto 8)="1100"  OR opcode(11 downto 8)="0100" THEN       --CMPI, SUBI
1514 
                                                                setaddsub <= '0';
1515 
                                                        END IF;
1516 
                                                END IF;
1517 
                                        END IF;
1518 
                                END IF;
1519 
                        END IF;
1520 
 
1521 
-- 0001, 0010, 0011 -----------------------------------------------------------------
1522 
                        WHEN "0001"|"0010"|"0011" =>                            --move.b, move.l, move.w
1523 
                                set_exec_MOVE <= '1';
1524 
                                IF opcode(8 downto 6)="001" THEN
1525 
                                        no_Flags <= '1';
1526 
                                END IF;
1527 
                                IF opcode(5 downto 4)="00" THEN --Dn, An
1528 
                                        regdirectsource <= '1';
1529 
                                END IF;
1530 
                                CASE opcode(13 downto 12) IS
1531 
                                        WHEN "01" => datatype <= "00";          --Byte
1532 
                                        WHEN "10" => datatype <= "10";          --Long
1533 
                                        WHEN OTHERS => datatype <= "01";        --Word
1534 
                                END CASE;
1535 
                                source_lowbits <= '1';                                  -- Dn=>  An=>
1536 
                                IF opcode(3)='1' THEN
1537 
                                        source_areg <= '1';
1538 
                                END IF;
1539 
                                IF getbrief='1' AND nextpass='1' THEN   -- =>(d16,An)  =>(d8,An,Xn)
1540 
                                        set_mem_rega <= '1';
1541 
                                END IF;
1542 
 
1543 
                                IF execOPC='1' AND opcode(8 downto 7)="00" THEN
1544 
                                        Regwrena <= '1';
1545 
                                END IF;
1546 
 
1547 
                                IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
1548 
                                        dest_hbits <= '1';
1549 
                                        IF opcode(8 downto 6)/="000" THEN
1550 
                                                dest_areg <= '1';
1551 
                                        END IF;
1552 
                                END IF;
1553 
 
1554 
                                IF decodeOPC='1' THEN
1555 
                                        ea_build <= '1';
1556 
                                END IF;
1557 
 
1558 
                                IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
1559 
                                        CASE opcode(8 downto 6) IS              --destination
1560 
--                                              WHEN "000" =>                                           --Dn
1561 
--                                              WHEN "001" =>                                           --An
1562 
                                                WHEN "010"|"011"|"100" =>                                       --destination -(an)+
1563 
                                                        IF opcode(7)='1' THEN
1564 
                                                                set_mem_rega <= '1';
1565 
                                                        ELSE
1566 
                                                                set_mem_addsub <= '1';
1567 
                                                        END IF;
1568 
                                                        IF opcode(6)='1' THEN   --(An)+
1569 
                                                                postadd <= '1';
1570 
                                                                IF opcode(11 downto 9)="111" THEN
1571 
                                                                        use_SP <= '1';
1572 
                                                                END IF;
1573 
                                                        END IF;
1574 
                                                        IF opcode(8)='1' THEN   -- -(An)
1575 
                                                                presub <= '1';
1576 
                                                                IF opcode(11 downto 9)="111" THEN
1577 
                                                                        use_SP <= '1';
1578 
                                                                END IF;
1579 
                                                        END IF;
1580 
                                                        IF opcode(7 downto 6)/="10" THEN
1581 
                                                                regwrena <= '1';
1582 
                                                        END IF;
1583 
                                                        setstate <= "11";
1584 
                                                        next_micro_state <= nop;
1585 
                                                WHEN "101" =>                           --(d16,An)
1586 
                                                        next_micro_state <= st_dAn1;
1587 
                                                        set_mem_regA <= '1';
1588 
                                                        setgetbrief <= '1';
1589 
                                                WHEN "110" =>                           --(d8,An,Xn)
1590 
                                                        next_micro_state <= st_AnXn1;
1591 
                                                        set_mem_regA <= '1';
1592 
                                                        setgetbrief <= '1';
1593 
                                                WHEN "111" =>
1594 
                                                        CASE opcode(11 downto 9) IS
1595 
                                                                WHEN "000" =>                           --(xxxx).w
1596 
                                                                        next_micro_state <= st_nn;
1597 
                                                                WHEN "001" =>                           --(xxxx).l
1598 
                                                                        longreaddirect <= '1';
1599 
                                                                        next_micro_state <= st_nn;
1600 
                                                                WHEN OTHERS =>
1601 
                                                        END CASE;
1602 
                                                WHEN OTHERS =>
1603 
                                        END CASE;
1604 
                                END IF;
1605 
-- 0100 ----------------------------------------------------------------------------
1606 
                        WHEN "0100" =>                          --rts_group
1607 
                                IF opcode(8)='1' THEN           --lea
1608 
                                        IF opcode(6)='1' THEN           --lea
1609 
                                                IF opcode(7)='1' THEN
1610 
                                                        ea_only <= '1';
1611 
                                                        IF opcode(5 downto 3)="010" THEN        --lea (Am),An
1612 
                                                                set_exec_move <='1';
1613 
                                                                no_Flags <='1';
1614 
                                                                dest_areg <= '1';
1615 
                                                                dest_hbits <= '1';
1616 
                                                                source_lowbits <= '1';
1617 
                                                                source_areg <= '1';
1618 
                                                                IF execOPC='1' THEN
1619 
                                                                        Regwrena <= '1';
1620 
                                                                END IF;
1621 
                                                        ELSE
1622 
                                                                IF decodeOPC='1' THEN
1623 
                                                                        ea_build <= '1';
1624 
                                                                END IF;
1625 
                                                        END IF;
1626 
                                                        IF get_ea_now='1' THEN
1627 
                                                                dest_areg <= '1';
1628 
                                                                dest_hbits <= '1';
1629 
                                                                regwrena <= '1';
1630 
                                                        END IF;
1631 
                                                ELSE
1632 
                                                        trap_illegal <= '1';
1633 
                                                        trapmake <= '1';
1634 
                                                END IF;
1635 
                                        ELSE                                                            --chk
1636 
                                                IF opcode(7)='1' THEN
1637 
                                                        set_exec_ADD <= '1';
1638 
                                                        IF decodeOPC='1' THEN
1639 
                                                                ea_build <= '1';
1640 
                                                        END IF;
1641 
                                                        datatype <= "01";       --Word
1642 
                                                        IF execOPC='1' THEN
1643 
                                                                setaddsub <= '0';
1644 
--first alternative
1645 
                                                                ea_data_OP1 <= '1';
1646 
                                                                IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
1647 
                                        --                              trap_chk <= '1';        --first I must change the Trap System
1648 
                                        --                              trapmake <= '1';
1649 
                                                                END IF;
1650 
--second alternative
1651 
--                                                              IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
1652 
--                                      --                              trap_chk <= '1';        --first I must change the Trap System
1653 
--                                      --                              trapmake <= '1';
1654 
--                                                              END IF;
1655 
--                                                              dest_hbits <= '1';
1656 
--                                                              source_lowbits <='1';
1657 
                                                        END IF;
1658 
                                                ELSE
1659 
                                                        trap_illegal <= '1';            -- chk long for 68020
1660 
                                                        trapmake <= '1';
1661 
                                                END IF;
1662 
                                        END IF;
1663 
                                ELSE
1664 
                                        CASE opcode(11 downto 9) IS
1665 
                                                WHEN "000"=>
1666 
                                                        IF decodeOPC='1' THEN
1667 
                                                                ea_build <= '1';
1668 
                                                        END IF;
1669 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move from SR
1670 
                                                                set_exec_MOVESR <= '1';
1671 
                                                                datatype <= "01";
1672 
                                                                write_back <='1';                                                       -- im 68000 wird auch erst gelesen
1673 
                                                                IF execOPC='1' THEN
1674 
                                                                        IF endOPC='1' THEN
1675 
                                                                                Regwrena <= '1';
1676 
                                                                        END IF;
1677 
                                                                END IF;
1678 
                                                        ELSE                                                                                    --negx
1679 
                                                                use_XFlag <= '1';
1680 
                                                                write_back <='1';
1681 
                                                                set_exec_ADD <= '1';
1682 
                                                                setaddsub <='0';
1683 
                                                                IF execOPC='1' THEN
1684 
                                                                        source_lowbits <= '1';
1685 
                                                                        OP1out_zero <= '1';
1686 
                                                                        IF endOPC='1' THEN
1687 
                                                                                Regwrena <= '1';
1688 
                                                                        END IF;
1689 
                                                                END IF;
1690 
                                                        END IF;
1691 
                                                WHEN "001"=>
1692 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move from CCR 68010
1693 
                                                                trap_illegal <= '1';
1694 
                                                                trapmake <= '1';
1695 
                                                        ELSE                                                                                    --clr
1696 
                                                                IF decodeOPC='1' THEN
1697 
                                                                        ea_build <= '1';
1698 
                                                                END IF;
1699 
                                                                write_back <='1';
1700 
                                                                set_exec_AND <= '1';
1701 
                                                                IF execOPC='1' THEN
1702 
                                                                        OP1out_zero <= '1';
1703 
                                                                        IF endOPC='1' THEN
1704 
                                                                                Regwrena <= '1';
1705 
                                                                        END IF;
1706 
                                                                END IF;
1707 
                                                        END IF;
1708 
                                                WHEN "010"=>
1709 
                                                        IF decodeOPC='1' THEN
1710 
                                                                ea_build <= '1';
1711 
                                                        END IF;
1712 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move to CCR
1713 
                                                                set_exec_MOVE <= '1';
1714 
                                                                datatype <= "01";
1715 
                                                                IF execOPC='1' THEN
1716 
                                                                        source_lowbits <= '1';
1717 
                                                                        to_SR <= '1';
1718 
                                                                END IF;
1719 
                                                        ELSE                                                                                    --neg
1720 
                                                                write_back <='1';
1721 
                                                                set_exec_ADD <= '1';
1722 
                                                                setaddsub <='0';
1723 
                                                                IF execOPC='1' THEN
1724 
                                                                        source_lowbits <= '1';
1725 
                                                                        OP1out_zero <= '1';
1726 
                                                                        IF endOPC='1' THEN
1727 
                                                                                Regwrena <= '1';
1728 
                                                                        END IF;
1729 
                                                                END IF;
1730 
                                                        END IF;
1731 
                                                WHEN "011"=>                                                                            --not, move toSR
1732 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move to SR
1733 
                                                                IF SVmode='1' THEN
1734 
                                                                        IF decodeOPC='1' THEN
1735 
                                                                                ea_build <= '1';
1736 
                                                                        END IF;
1737 
                                                                        set_exec_MOVE <= '1';
1738 
                                                                        datatype <= "01";
1739 
                                                                        IF execOPC='1' THEN
1740 
                                                                                source_lowbits <= '1';
1741 
                                                                                to_SR <= '1';
1742 
                                                                        END IF;
1743 
                                                                ELSE
1744 
                                                                        trap_priv <= '1';
1745 
                                                                        trapmake <= '1';
1746 
                                                                END IF;
1747 
                                                        ELSE                                                                                    --not
1748 
                                                                IF decodeOPC='1' THEN
1749 
                                                                        ea_build <= '1';
1750 
                                                                END IF;
1751 
                                                                write_back <='1';
1752 
                                                                set_exec_EOR <= '1';
1753 
                                                                IF execOPC='1' THEN
1754 
                                                                        OP2out_one <= '1';
1755 
                                                                        ea_data_OP1 <= '1';
1756 
                                                                        IF endOPC='1' THEN
1757 
                                                                                Regwrena <= '1';
1758 
                                                                        END IF;
1759 
                                                                END IF;
1760 
                                                        END IF;
1761 
                                                WHEN "100"|"110"=>
1762 
                                                        IF opcode(7)='1' THEN                   --movem, ext
1763 
                                                                IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN              --ext
1764 
                                                                        source_lowbits <= '1';
1765 
                                                                        IF decodeOPC='1' THEN
1766 
                                                                                set_exec_EXT <= '1';
1767 
                                                                                set_exec_move <= '1';
1768 
                                                                        END IF;
1769 
                                                                        IF opcode(6)='0' THEN
1770 
                                                                                datatype <= "01";               --WORD
1771 
                                                                        END IF;
1772 
                                                                        IF execOPC='1' THEN
1773 
                                                                                regwrena <= '1';
1774 
                                                                        END IF;
1775 
                                                                ELSE                                                                                                    --movem
1776 
--                                                              IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN      --MOVEM
1777 
                                                                        ea_only <= '1';
1778 
                                                                        IF decodeOPC='1' THEN
1779 
                                                                                datatype <= "01";               --Word
1780 
                                                                                set_get_movem_mask <='1';
1781 
                                                                                set_get_extendedOPC <='1';
1782 
 
1783 
                                                                                IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
1784 
                                                                                        set_mem_rega <= '1';
1785 
                                                                                        setstate <= "01";
1786 
                                                                                        IF opcode(10)='0' THEN
1787 
                                                                                                set_movem_busy <='1';
1788 
                                                                                        ELSE
1789 
                                                                                                next_micro_state <= movem;
1790 
                                                                                        END IF;
1791 
                                                                                ELSE
1792 
                                                                                        ea_build <= '1';
1793 
                                                                                END IF;
1794 
 
1795 
                                                                        ELSE
1796 
                                                                                IF opcode(6)='0' THEN
1797 
                                                                                        datatype <= "01";               --Word
1798 
                                                                                END IF;
1799 
                                                                        END IF;
1800 
                                                                        IF execOPC='1' THEN
1801 
                                                                                IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
1802 
                                                                                        regwrena <= '1';
1803 
                                                                                        save_memaddr <= '1';
1804 
                                                                                END IF;
1805 
                                                                        END IF;
1806 
                                                                        IF get_ea_now='1' THEN
1807 
                                                                                set_movem_busy <= '1';
1808 
                                                                                IF opcode(10)='0' THEN
1809 
                                                                                        setstate <="01";
1810 
                                                                                ELSE
1811 
                                                                                        setstate <="10";
1812 
                                                                                END IF;
1813 
                                                                        END IF;
1814 
                                                                                IF opcode(5 downto 3)="100" THEN
1815 
                                                                                        movem_presub <= '1';
1816 
                                                                                END IF;
1817 
                                                                                IF movem_addr='1' THEN
1818 
                                                                                        IF opcode(10)='1' THEN
1819 
                                                                                                regwrena <= '1';
1820 
                                                                                        END IF;
1821 
                                                                                END IF;
1822 
                                                                                IF movem_busy='1' THEN
1823 
                                                                                        IF opcode(10)='0' THEN
1824 
                                                                                                setstate <="11";
1825 
                                                                                        ELSE
1826 
                                                                                                setstate <="10";
1827 
                                                                                        END IF;
1828 
                                                                                END IF;
1829 
                                                                END IF;
1830 
                                                        ELSE
1831 
                                                                IF opcode(10)='1' THEN                                          --MUL, DIV 68020
1832 
                                                                        trap_illegal <= '1';
1833 
                                                                        trapmake <= '1';
1834 
                                                                ELSE                                                    --pea, swap
1835 
                                                                        IF opcode(6)='1' THEN
1836 
                                                                                datatype <= "10";
1837 
                                                                                IF opcode(5 downto 3)="000" THEN                --swap
1838 
                                                                                        IF execOPC='1' THEN
1839 
                                                                                                exec_swap <= '1';
1840 
                                                                                                regwrena <= '1';
1841 
                                                                                        END IF;
1842 
                                                                                ELSIF opcode(5 downto 3)="001" THEN             --bkpt
1843 
 
1844 
                                                                                ELSE                                                                    --pea
1845 
                                                                                        ea_only <= '1';
1846 
                                                                                        IF decodeOPC='1' THEN
1847 
                                                                                                ea_build <= '1';
1848 
                                                                                        END IF;
1849 
                                                                                        IF nextpass='1' AND micro_state=idle THEN
1850 
                                                                                                presub <= '1';
1851 
                                                                                                setstackaddr <='1';
1852 
                                                                                                set_mem_addsub <= '1';
1853 
                                                                                                setstate <="11";
1854 
                                                                                                next_micro_state <= nop;
1855 
                                                                                        END IF;
1856 
                                                                                        IF get_ea_now='1' THEN
1857 
                                                                                                setstate <="01";
1858 
                                                                                        END IF;
1859 
                                                                                END IF;
1860 
                                                                        ELSE                                                            --nbcd
1861 
                                                                                IF decodeOPC='1' THEN           --nbcd
1862 
                                                                                        ea_build <= '1';
1863 
                                                                                END IF;
1864 
                                                                                use_XFlag <= '1';
1865 
                                                                                write_back <='1';
1866 
                                                                                set_exec_ADD <= '1';
1867 
                                                                                set_exec_SBCD <= '1';
1868 
                                                                                IF execOPC='1' THEN
1869 
                                                                                        source_lowbits <= '1';
1870 
                                                                                        OP1out_zero <= '1';
1871 
                                                                                        IF endOPC='1' THEN
1872 
                                                                                                Regwrena <= '1';
1873 
                                                                                        END IF;
1874 
                                                                                END IF;
1875 
                                                                        END IF;
1876 
                                                                END IF;
1877 
                                                        END IF;
1878 
 
1879 
                                                WHEN "101"=>                                            --tst, tas
1880 
                                                        IF opcode(7 downto 2)="111111" THEN   --4AFC illegal
1881 
                                                                trap_illegal <= '1';
1882 
                                                                trapmake <= '1';
1883 
                                                        ELSE
1884 
                                                                IF decodeOPC='1' THEN
1885 
                                                                        ea_build <= '1';
1886 
                                                                END IF;
1887 
                                                                IF execOPC='1' THEN
1888 
                                                                        dest_hbits <= '1';                              --for Flags
1889 
                                                                        source_lowbits <= '1';
1890 
                        --                                              IF opcode(3)='1' THEN                   --MC68020...
1891 
                        --                                                      source_areg <= '1';
1892 
                        --                                              END IF;
1893 
                                                                END IF;
1894 
                                                                set_exec_MOVE <= '1';
1895 
                                                                IF opcode(7 downto 6)="11" THEN         --tas
1896 
                                                                        set_exec_tas <= '1';
1897 
                                                                        write_back <= '1';
1898 
                                                                        datatype <= "00";                               --Byte
1899 
                                                                        IF execOPC='1' AND endOPC='1' THEN
1900 
                                                                                regwrena <= '1';
1901 
                                                                        END IF;
1902 
                                                                END IF;
1903 
                                                        END IF;
1904 
--                                              WHEN "110"=>
1905 
                                                WHEN "111"=>                                    --4EXX
1906 
                                                        IF opcode(7)='1' THEN           --jsr, jmp
1907 
                                                                datatype <= "10";
1908 
                                                                ea_only <= '1';
1909 
                                                                IF nextpass='1' AND micro_state=idle THEN
1910 
                                                                        presub <= '1';
1911 
                                                                        setstackaddr <='1';
1912 
                                                                        set_mem_addsub <= '1';
1913 
                                                                        setstate <="11";
1914 
                                                                        next_micro_state <= nop;
1915 
                                                                END IF;
1916 
                                                                IF decodeOPC='1' THEN
1917 
                                                                        ea_build <= '1';
1918 
                                                                END IF;
1919 
                                                                IF get_ea_now='1' THEN                                  --jsr
1920 
                                                                        IF opcode(6)='0' THEN
1921 
                                                                                setstate <="01";
1922 
                                                                        END IF;
1923 
                                                                        ea_to_pc <= '1';
1924 
                                                                        IF opcode(5 downto 1)="11100" THEN
1925 
                                                                                writePC_add <= '1';
1926 
                                                                        ELSE
1927 
                                                                                writePC <= '1';
1928 
                                                                        END IF;
1929 
                                                                END IF;
1930 
                                                        ELSE                                            --
1931 
                                                                CASE opcode(6 downto 0) IS
1932 
                                                                        WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"|           --trap
1933 
                                                                             "1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" =>         --trap
1934 
                                                                                        trap_trap <='1';
1935 
                                                                                        trapmake <= '1';
1936 
                                                                        WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" =>         --link
1937 
                                                                                datatype <= "10";
1938 
                                                                                IF decodeOPC='1' THEN
1939 
                                                                                        next_micro_state <= link;
1940 
                                                                                        set_exec_MOVE <= '1';                                           --für displacement
1941 
                                                                                        presub <= '1';
1942 
                                                                                        setstackaddr <='1';
1943 
                                                                                        set_mem_addsub <= '1';
1944 
                                                                                        source_lowbits <= '1';
1945 
                                                                                        source_areg <= '1';
1946 
                                                                                END IF;
1947 
                                                                                IF execOPC='1' THEN
1948 
                                                                                        setstackaddr <='1';
1949 
                                                                                        regwrena <= '1';
1950 
                                                                                END IF;
1951 
 
1952 
                                                                        WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" =>         --unlink
1953 
                                                                                datatype <= "10";
1954 
                                                                                IF decodeOPC='1' THEN
1955 
                                                                                        setstate <= "10";
1956 
                                                                                        set_mem_rega <= '1';
1957 
                                                                                ELSIF execOPC='1' THEN
1958 
                                                                                        regwrena <= '1';
1959 
                                                                                        exec_exg <= '1';
1960 
                                                                                ELSE
1961 
                                                                                        setstackaddr <='1';
1962 
                                                                                        regwrena <= '1';
1963 
                                                                                        get_ea_now <= '1';
1964 
                                                                                        ea_only <= '1';
1965 
                                                                                END IF;
1966 
 
1967 
                                                                        WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" =>         --move An,USP
1968 
                                                                                IF SVmode='1' THEN
1969 
                                                                                        no_Flags <= '1';
1970 
                                                                                        to_USP <= '1';
1971 
                                                                                        setstackaddr <= '1';
1972 
                                                                                        source_lowbits <= '1';
1973 
                                                                                        source_areg <= '1';
1974 
                                                                                        set_exec_MOVE <= '1';
1975 
                                                                                        datatype <= "10";
1976 
                                                                                        IF execOPC='1' THEN
1977 
                                                                                                regwrena <= '1';
1978 
                                                                                        END IF;
1979 
                                                                                ELSE
1980 
                                                                                        trap_priv <= '1';
1981 
                                                                                        trapmake <= '1';
1982 
                                                                                END IF;
1983 
                                                                        WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" =>         --move USP,An
1984 
                                                                                IF SVmode='1' THEN
1985 
                                                                                        no_Flags <= '1';
1986 
                                                                                        from_USP <= '1';
1987 
                                                                                        set_exec_MOVE <= '1';
1988 
                                                                                        datatype <= "10";
1989 
                                                                                        IF execOPC='1' THEN
1990 
                                                                                                regwrena <= '1';
1991 
                                                                                        END IF;
1992 
                                                                                ELSE
1993 
                                                                                        trap_priv <= '1';
1994 
                                                                                        trapmake <= '1';
1995 
                                                                                END IF;
1996 
 
1997 
                                                                        WHEN "1110000" =>                                       --reset
1998 
                                                                                IF SVmode='0' THEN
1999 
                                                                                        trap_priv <= '1';
2000 
                                                                                        trapmake <= '1';
2001 
                                                                                END IF;
2002 
 
2003 
                                                                        WHEN "1110001" =>                                       --nop
2004 
 
2005 
                                                                        WHEN "1110010" =>                                       --stop
2006 
                                                                                IF SVmode='0' THEN
2007 
                                                                                        trap_priv <= '1';
2008 
                                                                                        trapmake <= '1';
2009 
                                                                                ELSE
2010 
                                                                                        IF decodeOPC='1' THEN
2011 
                                                                                                setnextpass <= '1';
2012 
                                                                                                set_directSR <= '1';
2013 
                                                                                                set_stop <= '1';
2014 
                                                                                        END IF;
2015 
                                                                                END IF;
2016 
 
2017 
                                                                        WHEN "1110011" =>                                                                       --rte
2018 
                                                                                IF SVmode='1' THEN
2019 
                                                                                        IF decodeOPC='1' THEN
2020 
                                                                                                datatype <= "01";
2021 
                                                                                                setstate <= "10";
2022 
                                                                                                postadd <= '1';
2023 
                                                                                                setstackaddr <= '1';
2024 
                                                                                                set_mem_rega <= '1';
2025 
                                                                                                set_directSR <= '1';
2026 
                                                                                                next_micro_state <= rte;
2027 
                                                                                        END IF;
2028 
                                                                                ELSE
2029 
                                                                                        trap_priv <= '1';
2030 
                                                                                        trapmake <= '1';
2031 
                                                                                END IF;
2032 
 
2033 
                                                                        WHEN "1110101" =>                                                                       --rts
2034 
                                                                                IF decodeOPC='1' THEN
2035 
                                                                                        datatype <= "10";
2036 
                                                                                        setstate <= "10";
2037 
                                                                                        postadd <= '1';
2038 
                                                                                        setstackaddr <= '1';
2039 
                                                                                        set_mem_rega <= '1';
2040 
                                                                                        set_directPC <= '1';
2041 
                                                                                        next_micro_state <= nop;
2042 
                                                                                END IF;
2043 
 
2044 
                                                                        WHEN "1110110" =>                                                                       --trapv
2045 
                                                                                IF Flags(1)='1' THEN
2046 
                                                                                        trap_trapv <= '1';
2047 
                                                                                        trapmake <= '1';
2048 
                                                                                END IF;
2049 
 
2050 
                                                                        WHEN "1110111" =>                                                                       --rtr
2051 
                                                                                IF decodeOPC='1' THEN
2052 
                                                                                        datatype <= "01";
2053 
                                                                                        setstate <= "10";
2054 
                                                                                        postadd <= '1';
2055 
                                                                                        setstackaddr <= '1';
2056 
                                                                                        set_mem_rega <= '1';
2057 
                                                                                        set_directCCR <= '1';
2058 
                                                                                        next_micro_state <= rte;
2059 
                                                                                END IF;
2060 
 
2061 
 
2062 
                                                                        WHEN OTHERS =>
2063 
                                                                                trap_illegal <= '1';
2064 
                                                                                trapmake <= '1';
2065 
                                                                END CASE;
2066 
                                                        END IF;
2067 
                                                WHEN OTHERS => null;
2068 
                                        END CASE;
2069 
                                END IF;
2070 
 
2071 
-- 0101 ----------------------------------------------------------------------------
2072 
                        WHEN "0101" =>                                                          --subq, addq
2073 
 
2074 
                                        IF opcode(7 downto 6)="11" THEN --dbcc
2075 
                                                IF opcode(5 downto 3)="001" THEN --dbcc
2076 
                                                        datatype <= "01";                       --Word
2077 
                                                        IF decodeOPC='1' THEN
2078 
                                                                next_micro_state <= nop;
2079 
                                                                OP2out_one <= '1';
2080 
                                                                IF condition='0' THEN
2081 
                                                                        Regwrena <= '1';
2082 
                                                                        IF c_in(2)='1' THEN
2083 
                                                                                next_micro_state <= dbcc1;
2084 
                                                                        END IF;
2085 
                                                                END IF;
2086 
                                                                data_is_source <= '1';
2087 
                                                        END IF;
2088 
                                                ELSE                            --Scc
2089 
                                                        datatype <= "00";                       --Byte
2090 
                                                        write_back <= '1';
2091 
                                                        IF decodeOPC='1' THEN
2092 
                                                                ea_build <= '1';
2093 
                                                        END IF;
2094 
                                                        IF condition='0' THEN
2095 
                                                                set_exec_Scc <= '1';
2096 
                                                        END IF;
2097 
                                                        IF execOPC='1' THEN
2098 
                                                                IF condition='1' THEN
2099 
                                                                        OP2out_one <= '1';
2100 
                                                                        exec_EXG <= '1';
2101 
                                                                ELSE
2102 
                                                                        OP1out_zero <= '1';
2103 
                                                                END IF;
2104 
                                                                IF endOPC='1' THEN
2105 
                                                                        Regwrena <= '1';
2106 
                                                                END IF;
2107 
                                                        END IF;
2108 
                                                END IF;
2109 
                                        ELSE                                    --addq, subq
2110 
                                                IF decodeOPC='1' THEN
2111 
                                                        ea_build <= '1';
2112 
                                                END IF;
2113 
                                                IF opcode(5 downto 3)="001" THEN
2114 
                                                        no_Flags <= '1';
2115 
                                                END IF;
2116 
                                                write_back <= '1';
2117 
                                                set_exec_ADDQ <= '1';
2118 
                                                set_exec_ADD <= '1';
2119 
                                                IF execOPC='1' THEN
2120 
                                                        ea_data_OP1 <= '1';
2121 
                                                        IF endOPC='1' THEN
2122 
                                                                Regwrena <= '1';
2123 
                                                        END IF;
2124 
                                                        IF opcode(8)='1' THEN
2125 
                                                                setaddsub <= '0';
2126 
                                                        END IF;
2127 
                                                END IF;
2128 
                                        END IF;
2129 
 
2130 
-- 0110 ----------------------------------------------------------------------------
2131 
                        WHEN "0110" =>                          --bra,bsr,bcc
2132 
                                datatype <= "10";
2133 
 
2134 
                                IF micro_state=idle THEN
2135 
                                        IF opcode(11 downto 8)="0001" THEN              --bsr
2136 
                                                IF opcode(7 downto 0)="00000000" THEN
2137 
                                                        next_micro_state <= bsr1;
2138 
                                                ELSE
2139 
                                                        next_micro_state <= bsr2;
2140 
                                                        setstate <= "01";
2141 
                                                END IF;
2142 
                                                presub <= '1';
2143 
                                                setstackaddr <='1';
2144 
                                                set_mem_addsub <= '1';
2145 
                                        ELSE                                                                    --bra
2146 
                                                IF opcode(7 downto 0)="00000000" THEN
2147 
                                                        next_micro_state <= bra1;
2148 
                                                END IF;
2149 
                                                IF condition='1' THEN
2150 
                                                        TG68_PC_br8 <= '1';
2151 
                                                END IF;
2152 
                                        END IF;
2153 
                                END IF;
2154 
 
2155 
-- 0111 ----------------------------------------------------------------------------
2156 
                        WHEN "0111" =>                          --moveq
2157 
                                IF opcode(8)='0' THEN
2158 
                                        IF trap_interrupt='0' THEN
2159 
                                                datatype <= "10";               --Long
2160 
                                                Regwrena <= '1';
2161 
                                                set_exec_MOVEQ <= '1';
2162 
                                                set_exec_MOVE <= '1';
2163 
                                                dest_hbits <= '1';
2164 
                                        END IF;
2165 
                                ELSE
2166 
                                        trap_illegal <= '1';
2167 
                                        trapmake <= '1';
2168 
                                END IF;
2169 
 
2170 
-- 1000 ----------------------------------------------------------------------------
2171 
                        WHEN "1000" =>                                                          --or
2172 
                                IF opcode(7 downto 6)="11" THEN --divu, divs
2173 
                                        IF opcode(5 downto 4)="00" THEN --Dn, An
2174 
                                                regdirectsource <= '1';
2175 
                                        END IF;
2176 
                                        IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2177 
                                                set_exec_DIVU <= '1';
2178 
                                                setstate <="01";
2179 
                                                next_micro_state <= div1;
2180 
                                        END IF;
2181 
                                        IF decodeOPC='1' THEN
2182 
                                                ea_build <= '1';
2183 
                                        END IF;
2184 
                                        IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
2185 
                                                regwrena <= '1';
2186 
                                        END IF;
2187 
                                        IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
2188 
                                                dest_hbits <= '1';
2189 
                                                source_lowbits <='1';
2190 
                                        ELSE
2191 
                                                datatype <= "01";
2192 
                                        END IF;
2193 
 
2194 
 
2195 
                                ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --sbcd, pack , unpack
2196 
                                        IF opcode(7 downto 6)="00" THEN --sbcd
2197 
                                                use_XZFlag <= '1';
2198 
                                                set_exec_ADD <= '1';
2199 
                                                set_exec_SBCD <= '1';
2200 
                                                IF opcode(3)='1' THEN
2201 
                                                        write_back <= '1';
2202 
                                                        IF decodeOPC='1' THEN
2203 
                                                                set_direct_data <= '1';
2204 
                                                                setstate <= "10";
2205 
                                                                set_mem_addsub <= '1';
2206 
                                                                presub <= '1';
2207 
                                                                next_micro_state <= op_AxAy;
2208 
                                                        END IF;
2209 
                                                END IF;
2210 
                                                IF execOPC='1' THEN
2211 
                                                        ea_data_OP1 <= '1';
2212 
                                                        dest_hbits <= '1';
2213 
                                                        source_lowbits <='1';
2214 
                                                        IF endOPC='1' THEN
2215 
                                                                Regwrena <= '1';
2216 
                                                        END IF;
2217 
                                                END IF;
2218 
                                        ELSE                                                                    --pack, unpack
2219 
                                                trap_illegal <= '1';
2220 
                                                trapmake <= '1';
2221 
                                        END IF;
2222 
                                ELSE                                                                    --or
2223 
                                        set_exec_OR <= '1';
2224 
                                        IF opcode(8)='1' THEN
2225 
                                                 write_back <= '1';
2226 
                                        END IF;
2227 
                                        IF decodeOPC='1' THEN
2228 
                                                ea_build <= '1';
2229 
                                        END IF;
2230 
                                        IF execOPC='1' THEN
2231 
                                                IF endOPC='1' THEN
2232 
                                                        Regwrena <= '1';
2233 
                                                END IF;
2234 
                                                IF opcode(8)='1' THEN
2235 
                                                        ea_data_OP1 <= '1';
2236 
                                                ELSE
2237 
                                                        dest_hbits <= '1';
2238 
                                                        source_lowbits <='1';
2239 
                                                        IF opcode(3)='1' THEN
2240 
                                                                source_areg <= '1';
2241 
                                                        END IF;
2242 
                                                END IF;
2243 
                                        END IF;
2244 
                                END IF;
2245 
 
2246 
-- 1001, 1101 -----------------------------------------------------------------------
2247 
                        WHEN "1001"|"1101" =>                                           --sub, add
2248 
                                set_exec_ADD <= '1';
2249 
                                IF decodeOPC='1' THEN
2250 
                                        ea_build <= '1';
2251 
                                END IF;
2252 
                                IF opcode(8 downto 6)="011" THEN        --adda.w, suba.w
2253 
                                        datatype <= "01";       --Word
2254 
                                END IF;
2255 
                                IF execOPC='1' THEN
2256 
                                        IF endOPC='1' THEN
2257 
                                                Regwrena <= '1';
2258 
                                        END IF;
2259 
                                        IF opcode(14)='0' THEN
2260 
                                                setaddsub <= '0';
2261 
                                        END IF;
2262 
                                END IF;
2263 
                                IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN          --addx, subx
2264 
                                        use_XZFlag <= '1';
2265 
                                        IF opcode(3)='1' THEN
2266 
                                                write_back <= '1';
2267 
                                                IF decodeOPC='1' THEN
2268 
                                                        set_direct_data <= '1';
2269 
                                                        setstate <= "10";
2270 
                                                        set_mem_addsub <= '1';
2271 
                                                        presub <= '1';
2272 
                                                        next_micro_state <= op_AxAy;
2273 
                                                END IF;
2274 
                                        END IF;
2275 
                                        IF execOPC='1' THEN
2276 
                                                ea_data_OP1 <= '1';
2277 
                                                dest_hbits <= '1';
2278 
                                                source_lowbits <='1';
2279 
                                        END IF;
2280 
                                ELSE                                                                                                    --sub, add
2281 
                                        IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
2282 
                                                 write_back <= '1';
2283 
                                        END IF;
2284 
                                        IF execOPC='1' THEN
2285 
                                                IF      opcode(7 downto 6)="11" THEN    --adda, suba
2286 
                                                        no_Flags <= '1';
2287 
                                                        dest_areg <='1';
2288 
                                                        dest_hbits <= '1';
2289 
                                                        source_lowbits <='1';
2290 
                                                        IF opcode(3)='1' THEN
2291 
                                                                source_areg <= '1';
2292 
                                                        END IF;
2293 
                                                ELSE
2294 
                                                        IF opcode(8)='1' THEN
2295 
                                                                ea_data_OP1 <= '1';
2296 
                                                        ELSE
2297 
                                                                dest_hbits <= '1';
2298 
                                                                source_lowbits <='1';
2299 
                                                                IF opcode(3)='1' THEN
2300 
                                                                        source_areg <= '1';
2301 
                                                                END IF;
2302 
                                                        END IF;
2303 
                                                END IF;
2304 
                                        END IF;
2305 
                                END IF;
2306 
 
2307 
-- 1010 ----------------------------------------------------------------------------
2308 
                        WHEN "1010" =>                                                  --Trap 1010
2309 
                                trap_1010 <= '1';
2310 
                                trapmake <= '1';
2311 
-- 1011 ----------------------------------------------------------------------------
2312 
                        WHEN "1011" =>                                                  --eor, cmp
2313 
                                IF decodeOPC='1' THEN
2314 
                                        ea_build <= '1';
2315 
                                END IF;
2316 
                                IF opcode(8 downto 6)="011" THEN        --cmpa.w
2317 
                                        datatype <= "01";       --Word
2318 
                                        set_exec_CPMAW <= '1';
2319 
                                END IF;
2320 
                                IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN         --cmpm
2321 
                                        set_exec_CMP <= '1';
2322 
                                        IF decodeOPC='1' THEN
2323 
                                                set_direct_data <= '1';
2324 
                                                setstate <= "10";
2325 
                                                set_mem_rega <= '1';
2326 
                                                postadd <= '1';
2327 
                                                next_micro_state <= cmpm;
2328 
                                        END IF;
2329 
                                        IF execOPC='1' THEN
2330 
                                                ea_data_OP1 <= '1';
2331 
                                                setaddsub <= '0';
2332 
                                        END IF;
2333 
                                ELSE                                                                                                    --sub, add
2334 
                                        IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN      --eor
2335 
                                                set_exec_EOR <= '1';
2336 
                                                 write_back <= '1';
2337 
                                        ELSE                                    --cmp
2338 
                                                set_exec_CMP <= '1';
2339 
                                        END IF;
2340 
 
2341 
                                        IF execOPC='1' THEN
2342 
                                                IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN      --eor
2343 
                                                        ea_data_OP1 <= '1';
2344 
                                                        IF endOPC='1' THEN
2345 
                                                                Regwrena <= '1';
2346 
                                                        END IF;
2347 
                                                ELSE                                                                    --cmp
2348 
                                                        source_lowbits <='1';
2349 
                                                        IF opcode(3)='1' THEN
2350 
                                                                source_areg <= '1';
2351 
                                                        END IF;
2352 
                                                        IF      opcode(7 downto 6)="11" THEN    --cmpa
2353 
                                                                dest_areg <='1';
2354 
                                                        END IF;
2355 
                                                        dest_hbits <= '1';
2356 
                                                        setaddsub <= '0';
2357 
                                                END IF;
2358 
                                        END IF;
2359 
                                END IF;
2360 
 
2361 
-- 1100 ----------------------------------------------------------------------------
2362 
                        WHEN "1100" =>                                                          --and, exg
2363 
                                IF opcode(7 downto 6)="11" THEN --mulu, muls
2364 
                                        IF opcode(5 downto 4)="00" THEN --Dn, An
2365 
                                                regdirectsource <= '1';
2366 
                                        END IF;
2367 
                                        IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2368 
                                                set_exec_MULU <= '1';
2369 
                                                setstate <="01";
2370 
                                                next_micro_state <= mul1;
2371 
                                        END IF;
2372 
                                        IF decodeOPC='1' THEN
2373 
                                                ea_build <= '1';
2374 
                                        END IF;
2375 
                                        IF      execOPC='1' THEN
2376 
                                                regwrena <= '1';
2377 
                                        END IF;
2378 
                                        IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
2379 
                                                dest_hbits <= '1';
2380 
                                                source_lowbits <='1';
2381 
                                        ELSE
2382 
                                                datatype <= "01";
2383 
                                        END IF;
2384 
 
2385 
                                ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --exg, abcd
2386 
                                        IF opcode(7 downto 6)="00" THEN --abcd
2387 
                                                use_XZFlag <= '1';
2388 
--                                              datatype <= "00";               --ist schon default
2389 
                                                set_exec_ADD <= '1';
2390 
                                                set_exec_ABCD <= '1';
2391 
                                                IF opcode(3)='1' THEN
2392 
                                                        write_back <= '1';
2393 
                                                        IF decodeOPC='1' THEN
2394 
                                                                set_direct_data <= '1';
2395 
                                                                setstate <= "10";
2396 
                                                                set_mem_addsub <= '1';
2397 
                                                                presub <= '1';
2398 
                                                                next_micro_state <= op_AxAy;
2399 
                                                        END IF;
2400 
                                                END IF;
2401 
                                                IF execOPC='1' THEN
2402 
                                                        ea_data_OP1 <= '1';
2403 
                                                        dest_hbits <= '1';
2404 
                                                        source_lowbits <='1';
2405 
                                                        IF endOPC='1' THEN
2406 
                                                                Regwrena <= '1';
2407 
                                                        END IF;
2408 
                                                END IF;
2409 
                                        ELSE                                                                    --exg
2410 
                                                datatype <= "10";
2411 
                                                regwrena <= '1';
2412 
                                                IF opcode(6)='1' AND opcode(3)='1' THEN
2413 
                                                        dest_areg <= '1';
2414 
                                                        source_areg <= '1';
2415 
                                                END IF;
2416 
                                                IF decodeOPC='1' THEN
2417 
                                                        set_mem_rega <= '1';
2418 
                                                        exec_exg <= '1';
2419 
                                                ELSE
2420 
                                                        save_memaddr <= '1';
2421 
                                                        dest_hbits <= '1';
2422 
                                                END IF;
2423 
                                        END IF;
2424 
                                ELSE                                                                    --and
2425 
                                        set_exec_AND <= '1';
2426 
                                        IF opcode(8)='1' THEN
2427 
                                                 write_back <= '1';
2428 
                                        END IF;
2429 
                                        IF decodeOPC='1' THEN
2430 
                                                ea_build <= '1';
2431 
                                        END IF;
2432 
 
2433 
                                        IF execOPC='1' THEN
2434 
                                                IF endOPC='1' THEN
2435 
                                                        Regwrena <= '1';
2436 
                                                END IF;
2437 
                                                IF opcode(8)='1' THEN
2438 
                                                        ea_data_OP1 <= '1';
2439 
                                                ELSE
2440 
                                                        dest_hbits <= '1';
2441 
                                                        source_lowbits <='1';
2442 
                                                        IF opcode(3)='1' THEN
2443 
                                                                source_areg <= '1';
2444 
                                                        END IF;
2445 
                                                END IF;
2446 
                                        END IF;
2447 
                                END IF;
2448 
 
2449 
-- 1110 ----------------------------------------------------------------------------
2450 
                        WHEN "1110" =>                                                          --rotation
2451 
                                set_exec_ROT <= '1';
2452 
                                IF opcode(7 downto 6)="11" THEN
2453 
                                        datatype <= "01";
2454 
                                        rot_bits <= opcode(10 downto 9);
2455 
                                        ea_data_OP1 <= '1';
2456 
                                        write_back <= '1';
2457 
                                ELSE
2458 
                                        rot_bits <= opcode(4 downto 3);
2459 
                                        data_is_source <= '1';
2460 
                                END IF;
2461 
 
2462 
                                IF decodeOPC='1' THEN
2463 
                                        IF opcode(7 downto 6)="11" THEN
2464 
                                                ea_build <= '1';
2465 
                                        ELSE
2466 
                                                IF opcode(5)='1' THEN
2467 
                                                        IF OP2out(5 downto 0)/="000000" THEN
2468 
                                                                set_rot_cnt <= OP2out(5 downto 0);
2469 
                                                        ELSE
2470 
                                                                set_rot_nop <= '1';
2471 
                                                        END IF;
2472 
                                                ELSE
2473 
                                                        set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
2474 
                                                        IF opcode(11 downto 9)="000" THEN
2475 
                                                                set_rot_cnt(3) <='1';
2476 
                                                        ELSE
2477 
                                                                set_rot_cnt(3) <='0';
2478 
                                                        END IF;
2479 
                                                END IF;
2480 
                                        END IF;
2481 
                                END IF;
2482 
                                IF opcode(7 downto 6)/="11" THEN
2483 
                                        IF execOPC='1' AND rot_nop='0' THEN
2484 
                                                Regwrena <= '1';
2485 
                                                set_rot_cnt <= rot_cnt-1;
2486 
                                        END IF;
2487 
                                END IF;
2488 
 
2489 
--      ----------------------------------------------------------------------------
2490 
                        WHEN OTHERS =>
2491 
                                trap_1111 <= '1';
2492 
                                trapmake <= '1';
2493 
 
2494 
                END CASE;
2495 
 
2496 
--      END PROCESS;
2497 
 
2498 
-----------------------------------------------------------------------------
2499 
-- execute microcode
2500 
-----------------------------------------------------------------------------
2501 
--PROCESS (micro_state)
2502 
--      BEGIN
2503 
                IF Z_error='1'  THEN            -- divu by zero
2504 
                        trapmake <= '1';                        --wichtig für USP
2505 
                        IF trapd='0' THEN
2506 
                                writePC <= '1';
2507 
                        END IF;
2508 
                END IF;
2509 
 
2510 
                IF trapmake='1' AND trapd='0' THEN
2511 
                        next_micro_state <= trap1;
2512 
                        presub <= '1';
2513 
                        setstackaddr <='1';
2514 
                        set_mem_addsub <= '1';
2515 
                        setstate <= "11";
2516 
                        datatype <= "10";
2517 
                END IF;
2518 
 
2519 
                IF interrupt='1' THEN
2520 
                        next_micro_state <= int1;
2521 
                        setstate <= "10";
2522 
--                      datatype <= "01";               --wirkt sich auf Flags aus
2523 
                END IF;
2524 
 
2525 
                IF reset='0' THEN
2526 
                        micro_state <= init1;
2527 
                ELSIF rising_edge(clk) THEN
2528 
                IF clkena='1' THEN
2529 
                                trapd <= trapmake;
2530 
                                IF fetchOPC='1' THEN
2531 
                                        micro_state <= idle;
2532 
                                ELSE
2533 
                                        micro_state <= next_micro_state;
2534 
                                END IF;
2535 
                        END IF;
2536 
                END IF;
2537 
                        CASE micro_state IS
2538 
                                WHEN ld_nn =>           -- (nnnn).w/l=>
2539 
                                        get_ea_now <='1';
2540 
                                        setnextpass <= '1';
2541 
                                        setaddrlong <= '1';
2542 
 
2543 
                                WHEN st_nn =>           -- =>(nnnn).w/l
2544 
                                        setstate <= "11";
2545 
                                        setaddrlong <= '1';
2546 
                                        next_micro_state <= nop;
2547 
 
2548 
                                WHEN ld_dAn1 =>         -- d(An)=>, --d(PC)=>
2549 
                                        setstate <= "01";
2550 
                                        next_micro_state <= ld_dAn2;
2551 
                                WHEN ld_dAn2 =>         -- d(An)=>, --d(PC)=>
2552 
                                        get_ea_now <='1';
2553 
                                        setdisp <= '1';         --word
2554 
                                        setnextpass <= '1';
2555 
 
2556 
                                WHEN ld_AnXn1 =>                -- d(An,Xn)=>, --d(PC,Xn)=>
2557 
                                        setstate <= "01";
2558 
                                        next_micro_state <= ld_AnXn2;
2559 
                                WHEN ld_AnXn2 =>                -- d(An,Xn)=>, --d(PC,Xn)=>
2560 
                                        setdisp <= '1';         --byte
2561 
                                        setdispbyte <= '1';
2562 
                                        setstate <= "01";
2563 
                                        setbriefext <= '1';
2564 
                                        next_micro_state <= ld_AnXn3;
2565 
                                WHEN ld_AnXn3 =>
2566 
                                        get_ea_now <='1';
2567 
                                        setdisp <= '1';         --brief
2568 
                                        setdispbrief <= '1';
2569 
                                        setnextpass <= '1';
2570 
 
2571 
                                WHEN st_dAn1 =>         -- =>d(An)
2572 
                                        setstate <= "01";
2573 
                                        next_micro_state <= st_dAn2;
2574 
                                WHEN st_dAn2 =>         -- =>d(An)
2575 
                                        setstate <= "11";
2576 
                                        setdisp <= '1';         --word
2577 
                                        next_micro_state <= nop;
2578 
 
2579 
                                WHEN st_AnXn1 =>                -- =>d(An,Xn)
2580 
                                        setstate <= "01";
2581 
                                        next_micro_state <= st_AnXn2;
2582 
                                WHEN st_AnXn2 =>                -- =>d(An,Xn)
2583 
                                        setdisp <= '1';         --byte
2584 
                                        setdispbyte <= '1';
2585 
                                        setstate <= "01";
2586 
                                        setbriefext <= '1';
2587 
                                        next_micro_state <= st_AnXn3;
2588 
                                WHEN st_AnXn3 =>
2589 
                                        setstate <= "11";
2590 
                                        setdisp <= '1';         --brief
2591 
                                        setdispbrief <= '1';
2592 
                                        next_micro_state <= nop;
2593 
 
2594 
                                WHEN bra1 =>            --bra
2595 
                                        IF condition='1' THEN
2596 
                                                TG68_PC_br8 <= '1';     --pc+0000
2597 
                                                setstate <= "01";
2598 
                                                next_micro_state <= bra2;
2599 
                                        END IF;
2600 
                                WHEN bra2 =>            --bra
2601 
                                        TG68_PC_brw <= '1';
2602 
 
2603 
                                WHEN bsr1 =>            --bsr
2604 
                                        set_TG68_PC_dec <= '1';         --in 2 Takten -2
2605 
                                        setstate <= "01";
2606 
                                        next_micro_state <= bsr2;
2607 
                                WHEN bsr2 =>            --bsr
2608 
                                        IF TG68_PC_dec(0)='1' THEN
2609 
                                                TG68_PC_brw <= '1';
2610 
                                        ELSE
2611 
                                                TG68_PC_br8 <= '1';
2612 
                                        END IF;
2613 
                                        writePC <= '1';
2614 
                                        setstate <= "11";
2615 
                                        next_micro_state <= nop;
2616 
 
2617 
                                WHEN dbcc1 =>           --dbcc
2618 
                                        TG68_PC_nop <= '1';
2619 
                                        setstate <= "01";
2620 
                                        next_micro_state <= dbcc2;
2621 
                                WHEN dbcc2 =>           --dbcc
2622 
                                        TG68_PC_brw <= '1';
2623 
 
2624 
                                WHEN movem =>           --movem
2625 
                                        set_movem_busy <='1';
2626 
                                        setstate <= "10";
2627 
 
2628 
                                WHEN andi =>            --andi
2629 
                                        IF opcode(5 downto 4)/="00" THEN
2630 
                                                ea_build <= '1';
2631 
                                                setnextpass <= '1';
2632 
                                        END IF;
2633 
 
2634 
                                WHEN op_AxAy =>         -- op -(Ax),-(Ay)
2635 
                                        presub <= '1';
2636 
                                        dest_hbits <= '1';
2637 
                                        dest_areg <= '1';
2638 
                                        set_mem_addsub <= '1';
2639 
                                        setstate <= "10";
2640 
 
2641 
                                WHEN cmpm =>            -- cmpm (Ay)+,(Ax)+
2642 
                                        postadd <= '1';
2643 
                                        dest_hbits <= '1';
2644 
                                        dest_areg <= '1';
2645 
                                        set_mem_rega <= '1';
2646 
                                        setstate <= "10";
2647 
 
2648 
                                WHEN link =>            -- link
2649 
                                        setstate <="11";
2650 
                                        save_memaddr <= '1';
2651 
                                        regwrena <= '1';
2652 
 
2653 
                                WHEN int1 =>            -- interrupt
2654 
                                        presub <= '1';
2655 
                                        setstackaddr <='1';
2656 
                                        set_mem_addsub <= '1';
2657 
                                        setstate <= "11";
2658 
                                        datatype <= "10";
2659 
                                        next_micro_state <= int2;
2660 
                                WHEN int2 =>            -- interrupt
2661 
                                        presub <= '1';
2662 
                                        setstackaddr <='1';
2663 
                                        set_mem_addsub <= '1';
2664 
                                        setstate <= "11";
2665 
                                        datatype <= "01";
2666 
                                        writeSR <= '1';
2667 
                                        next_micro_state <= int3;
2668 
                                WHEN int3 =>            -- interrupt
2669 
                                        set_vectoraddr <= '1';
2670 
                                        datatype <= "10";
2671 
                                        set_directPC <= '1';
2672 
                                        setstate <= "10";
2673 
                                        next_micro_state <= int4;
2674 
                                WHEN int4 =>            -- interrupt
2675 
                                        datatype <= "10";
2676 
 
2677 
                                WHEN rte =>             -- RTE
2678 
                                        datatype <= "10";
2679 
                                        setstate <= "10";
2680 
                                        postadd <= '1';
2681 
                                        setstackaddr <= '1';
2682 
                                        set_mem_rega <= '1';
2683 
                                        set_directPC <= '1';
2684 
                                        next_micro_state <= nop;
2685 
 
2686 
                                WHEN trap1 =>           -- TRAP
2687 
                                        presub <= '1';
2688 
                                        setstackaddr <='1';
2689 
                                        set_mem_addsub <= '1';
2690 
                                        setstate <= "11";
2691 
                                        datatype <= "01";
2692 
                                        writeSR <= '1';
2693 
                                        next_micro_state <= trap2;
2694 
                                WHEN trap2 =>           -- TRAP
2695 
                                        set_vectoraddr <= '1';
2696 
                                        datatype <= "10";
2697 
                                        set_directPC <= '1';
2698 
--                                      longreaddirect <= '1';
2699 
                                        setstate <= "10";
2700 
                                        next_micro_state <= trap3;
2701 
                                WHEN trap3 =>           -- TRAP
2702 
                                        datatype <= "10";
2703 
 
2704 
                                WHEN movep1 =>          -- MOVEP d(An)
2705 
                                        setstate <= "01";
2706 
                                        IF opcode(6)='1' THEN
2707 
                                                set_movepl <= '1';
2708 
                                        END IF;
2709 
                                        next_micro_state <= movep2;
2710 
                                WHEN movep2 =>
2711 
                                        setdisp <= '1';
2712 
                                        IF opcode(7)='0' THEN
2713 
                                                setstate <= "10";
2714 
                                        ELSE
2715 
                                                setstate <= "11";
2716 
                                                wait_mem_byte <= '1';
2717 
                                        END IF;
2718 
                                        next_micro_state <= movep3;
2719 
                                WHEN movep3 =>
2720 
                                        IF opcode(6)='1' THEN
2721 
                                                set_movepw <= '1';
2722 
                                                next_micro_state <= movep4;
2723 
                                        END IF;
2724 
                                        IF opcode(7)='0' THEN
2725 
                                                setstate <= "10";
2726 
                                        ELSE
2727 
                                                setstate <= "11";
2728 
                                        END IF;
2729 
                                WHEN movep4 =>
2730 
                                        IF opcode(7)='0' THEN
2731 
                                                setstate <= "10";
2732 
                                        ELSE
2733 
                                                wait_mem_byte <= '1';
2734 
                                                setstate <= "11";
2735 
                                        END IF;
2736 
                                        next_micro_state <= movep5;
2737 
                                WHEN movep5 =>
2738 
                                        IF opcode(7)='0' THEN
2739 
                                                setstate <= "10";
2740 
                                        ELSE
2741 
                                                setstate <= "11";
2742 
                                        END IF;
2743 
 
2744 
                                WHEN init1 =>           -- init SP
2745 
                                        longreaddirect <= '1';
2746 
                                        next_micro_state <= init2;
2747 
                                WHEN init2 =>           -- init PC
2748 
                                        get_ea_now <='1';       --\
2749 
                                        ea_only <= '1';         ---  OP1in <= memaddr_in
2750 
                                        setaddrlong <= '1';     --   memaddr_in <= data_read
2751 
                                        regwrena <= '1';
2752 
                                        setstackaddr <='1';     --   dest_addr <= SP
2753 
                                        set_directPC <= '1';
2754 
                                        longreaddirect <= '1';
2755 
                                        next_micro_state <= nop;
2756 
 
2757 
                                WHEN mul1       =>              -- mulu
2758 
                                        set_exec_MULU <= '1';
2759 
                                        setstate <="01";
2760 
                                        next_micro_state <= mul2;
2761 
                                WHEN mul2       =>              -- mulu
2762 
                                        set_exec_MULU <= '1';
2763 
                                        setstate <="01";
2764 
                                        next_micro_state <= mul3;
2765 
                                WHEN mul3       =>              -- mulu
2766 
                                        set_exec_MULU <= '1';
2767 
                                        setstate <="01";
2768 
                                        next_micro_state <= mul4;
2769 
                                WHEN mul4       =>              -- mulu
2770 
                                        set_exec_MULU <= '1';
2771 
                                        setstate <="01";
2772 
                                        next_micro_state <= mul5;
2773 
                                WHEN mul5       =>              -- mulu
2774 
                                        set_exec_MULU <= '1';
2775 
                                        setstate <="01";
2776 
                                        next_micro_state <= mul6;
2777 
                                WHEN mul6       =>              -- mulu
2778 
                                        set_exec_MULU <= '1';
2779 
                                        setstate <="01";
2780 
                                        next_micro_state <= mul7;
2781 
                                WHEN mul7       =>              -- mulu
2782 
                                        set_exec_MULU <= '1';
2783 
                                        setstate <="01";
2784 
                                        next_micro_state <= mul8;
2785 
                                WHEN mul8       =>              -- mulu
2786 
                                        set_exec_MULU <= '1';
2787 
                                        setstate <="01";
2788 
                                        next_micro_state <= mul9;
2789 
                                WHEN mul9       =>              -- mulu
2790 
                                        set_exec_MULU <= '1';
2791 
                                        setstate <="01";
2792 
                                        next_micro_state <= mul10;
2793 
                                WHEN mul10      =>              -- mulu
2794 
                                        set_exec_MULU <= '1';
2795 
                                        setstate <="01";
2796 
                                        next_micro_state <= mul11;
2797 
                                WHEN mul11      =>              -- mulu
2798 
                                        set_exec_MULU <= '1';
2799 
                                        setstate <="01";
2800 
                                        next_micro_state <= mul12;
2801 
                                WHEN mul12      =>              -- mulu
2802 
                                        set_exec_MULU <= '1';
2803 
                                        setstate <="01";
2804 
                                        next_micro_state <= mul13;
2805 
                                WHEN mul13      =>              -- mulu
2806 
                                        set_exec_MULU <= '1';
2807 
                                        setstate <="01";
2808 
                                        next_micro_state <= mul14;
2809 
                                WHEN mul14      =>              -- mulu
2810 
                                        set_exec_MULU <= '1';
2811 
                                        setstate <="01";
2812 
                                        next_micro_state <= mul15;
2813 
                                WHEN mul15      =>              -- mulu
2814 
                                        set_exec_MULU <= '1';
2815 
 
2816 
                                WHEN div1 =>            -- divu
2817 
                                        IF OP2out(15 downto 0)=x"0000" THEN              --div zero
2818 
                                                set_Z_error <= '1';
2819 
                                        ELSE
2820 
                                                set_exec_DIVU <= '1';
2821 
                                                next_micro_state <= div2;
2822 
                                        END IF;
2823 
                                        setstate <="01";
2824 
                                WHEN div2       =>              -- divu
2825 
                                        set_exec_DIVU <= '1';
2826 
                                        setstate <="01";
2827 
                                        next_micro_state <= div3;
2828 
                                WHEN div3       =>              -- divu
2829 
                                        set_exec_DIVU <= '1';
2830 
                                        setstate <="01";
2831 
                                        next_micro_state <= div4;
2832 
                                WHEN div4       =>              -- divu
2833 
                                        set_exec_DIVU <= '1';
2834 
                                        setstate <="01";
2835 
                                        next_micro_state <= div5;
2836 
                                WHEN div5       =>              -- divu
2837 
                                        set_exec_DIVU <= '1';
2838 
                                        setstate <="01";
2839 
                                        next_micro_state <= div6;
2840 
                                WHEN div6       =>              -- divu
2841 
                                        set_exec_DIVU <= '1';
2842 
                                        setstate <="01";
2843 
                                        next_micro_state <= div7;
2844 
                                WHEN div7       =>              -- divu
2845 
                                        set_exec_DIVU <= '1';
2846 
                                        setstate <="01";
2847 
                                        next_micro_state <= div8;
2848 
                                WHEN div8       =>              -- divu
2849 
                                        set_exec_DIVU <= '1';
2850 
                                        setstate <="01";
2851 
                                        next_micro_state <= div9;
2852 
                                WHEN div9       =>              -- divu
2853 
                                        set_exec_DIVU <= '1';
2854 
                                        setstate <="01";
2855 
                                        next_micro_state <= div10;
2856 
                                WHEN div10      =>              -- divu
2857 
                                        set_exec_DIVU <= '1';
2858 
                                        setstate <="01";
2859 
                                        next_micro_state <= div11;
2860 
                                WHEN div11      =>              -- divu
2861 
                                        set_exec_DIVU <= '1';
2862 
                                        setstate <="01";
2863 
                                        next_micro_state <= div12;
2864 
                                WHEN div12      =>              -- divu
2865 
                                        set_exec_DIVU <= '1';
2866 
                                        setstate <="01";
2867 
                                        next_micro_state <= div13;
2868 
                                WHEN div13      =>              -- divu
2869 
                                        set_exec_DIVU <= '1';
2870 
                                        setstate <="01";
2871 
                                        next_micro_state <= div14;
2872 
                                WHEN div14      =>              -- divu
2873 
                                        set_exec_DIVU <= '1';
2874 
                                        setstate <="01";
2875 
                                        next_micro_state <= div15;
2876 
                                WHEN div15      =>              -- divu
2877 
                                        set_exec_DIVU <= '1';
2878 
 
2879 
                                WHEN OTHERS => null;
2880 
                        END CASE;
2881 
        END PROCESS;
2882 
 
2883 
-----------------------------------------------------------------------------
2884 
-- Conditions
2885 
-----------------------------------------------------------------------------
2886 
PROCESS (opcode, Flags)
2887 
        BEGIN
2888 
                CASE opcode(11 downto 8) IS
2889 
                        WHEN X"0" => condition <= '1';
2890 
                        WHEN X"1" => condition <= '0';
2891 
                        WHEN X"2" => condition <=  NOT Flags(0) AND NOT Flags(2);
2892 
                        WHEN X"3" => condition <= Flags(0) OR Flags(2);
2893 
                        WHEN X"4" => condition <= NOT Flags(0);
2894 
                        WHEN X"5" => condition <= Flags(0);
2895 
                        WHEN X"6" => condition <= NOT Flags(2);
2896 
                        WHEN X"7" => condition <= Flags(2);
2897 
                        WHEN X"8" => condition <= NOT Flags(1);
2898 
                        WHEN X"9" => condition <= Flags(1);
2899 
                        WHEN X"a" => condition <= NOT Flags(3);
2900 
                        WHEN X"b" => condition <= Flags(3);
2901 
                        WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
2902 
                        WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
2903 
                        WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
2904 
                        WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
2905 
                        WHEN OTHERS => null;
2906 
                END CASE;
2907 
        END PROCESS;
2908 
 
2909 
-----------------------------------------------------------------------------
2910 
-- Bits
2911 
-----------------------------------------------------------------------------
2912 
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
2913 
        BEGIN
2914 
                CASE opcode(7 downto 6) IS
2915 
                        WHEN "00" =>                                    --btst
2916 
                                                one_bit_out <= one_bit_in;
2917 
                        WHEN "01" =>                                    --bchg
2918 
                                                one_bit_out <= NOT one_bit_in;
2919 
                        WHEN "10" =>                                    --bclr
2920 
                                                one_bit_out <= '0';
2921 
                        WHEN "11" =>                                    --bset
2922 
                                                one_bit_out <= '1';
2923 
                        WHEN OTHERS => null;
2924 
                END CASE;
2925 
 
2926 
                IF opcode(8)='0' THEN
2927 
                        IF opcode(5 downto 4)="00" THEN
2928 
                                bit_number <= bit_number_reg(4 downto 0);
2929 
                        ELSE
2930 
                                bit_number <= "00"&bit_number_reg(2 downto 0);
2931 
                        END IF;
2932 
                ELSE
2933 
                        IF opcode(5 downto 4)="00" THEN
2934 
                                bit_number <= OP2out(4 downto 0);
2935 
                        ELSE
2936 
                                bit_number <= "00"&OP2out(2 downto 0);
2937 
                        END IF;
2938 
                END IF;
2939 
 
2940 
                bits_out <= OP1out;
2941 
                CASE bit_Number IS
2942 
                        WHEN "00000" => one_bit_in <= OP1out(0);
2943 
                                                        bits_out(0) <= one_bit_out;
2944 
                        WHEN "00001" => one_bit_in <= OP1out(1);
2945 
                                                        bits_out(1) <= one_bit_out;
2946 
                        WHEN "00010" => one_bit_in <= OP1out(2);
2947 
                                                        bits_out(2) <= one_bit_out;
2948 
                        WHEN "00011" => one_bit_in <= OP1out(3);
2949 
                                                        bits_out(3) <= one_bit_out;
2950 
                        WHEN "00100" => one_bit_in <= OP1out(4);
2951 
                                                        bits_out(4) <= one_bit_out;
2952 
                        WHEN "00101" => one_bit_in <= OP1out(5);
2953 
                                                        bits_out(5) <= one_bit_out;
2954 
                        WHEN "00110" => one_bit_in <= OP1out(6);
2955 
                                                        bits_out(6) <= one_bit_out;
2956 
                        WHEN "00111" => one_bit_in <= OP1out(7);
2957 
                                                        bits_out(7) <= one_bit_out;
2958 
                        WHEN "01000" => one_bit_in <= OP1out(8);
2959 
                                                        bits_out(8) <= one_bit_out;
2960 
                        WHEN "01001" => one_bit_in <= OP1out(9);
2961 
                                                        bits_out(9) <= one_bit_out;
2962 
                        WHEN "01010" => one_bit_in <= OP1out(10);
2963 
                                                        bits_out(10) <= one_bit_out;
2964 
                        WHEN "01011" => one_bit_in <= OP1out(11);
2965 
                                                        bits_out(11) <= one_bit_out;
2966 
                        WHEN "01100" => one_bit_in <= OP1out(12);
2967 
                                                        bits_out(12) <= one_bit_out;
2968 
                        WHEN "01101" => one_bit_in <= OP1out(13);
2969 
                                                        bits_out(13) <= one_bit_out;
2970 
                        WHEN "01110" => one_bit_in <= OP1out(14);
2971 
                                                        bits_out(14) <= one_bit_out;
2972 
                        WHEN "01111" => one_bit_in <= OP1out(15);
2973 
                                                        bits_out(15) <= one_bit_out;
2974 
                        WHEN "10000" => one_bit_in <= OP1out(16);
2975 
                                                        bits_out(16) <= one_bit_out;
2976 
                        WHEN "10001" => one_bit_in <= OP1out(17);
2977 
                                                        bits_out(17) <= one_bit_out;
2978 
                        WHEN "10010" => one_bit_in <= OP1out(18);
2979 
                                                        bits_out(18) <= one_bit_out;
2980 
                        WHEN "10011" => one_bit_in <= OP1out(19);
2981 
                                                        bits_out(19) <= one_bit_out;
2982 
                        WHEN "10100" => one_bit_in <= OP1out(20);
2983 
                                                        bits_out(20) <= one_bit_out;
2984 
                        WHEN "10101" => one_bit_in <= OP1out(21);
2985 
                                                        bits_out(21) <= one_bit_out;
2986 
                        WHEN "10110" => one_bit_in <= OP1out(22);
2987 
                                                        bits_out(22) <= one_bit_out;
2988 
                        WHEN "10111" => one_bit_in <= OP1out(23);
2989 
                                                        bits_out(23) <= one_bit_out;
2990 
                        WHEN "11000" => one_bit_in <= OP1out(24);
2991 
                                                        bits_out(24) <= one_bit_out;
2992 
                        WHEN "11001" => one_bit_in <= OP1out(25);
2993 
                                                        bits_out(25) <= one_bit_out;
2994 
                        WHEN "11010" => one_bit_in <= OP1out(26);
2995 
                                                        bits_out(26) <= one_bit_out;
2996 
                        WHEN "11011" => one_bit_in <= OP1out(27);
2997 
                                                        bits_out(27) <= one_bit_out;
2998 
                        WHEN "11100" => one_bit_in <= OP1out(28);
2999 
                                                        bits_out(28) <= one_bit_out;
3000 
                        WHEN "11101" => one_bit_in <= OP1out(29);
3001 
                                                        bits_out(29) <= one_bit_out;
3002 
                        WHEN "11110" => one_bit_in <= OP1out(30);
3003 
                                                        bits_out(30) <= one_bit_out;
3004 
                        WHEN "11111" => one_bit_in <= OP1out(31);
3005 
                                                        bits_out(31) <= one_bit_out;
3006 
                        WHEN OTHERS =>  null;
3007 
                END CASE;
3008 
        END PROCESS;
3009 
 
3010 
-----------------------------------------------------------------------------
3011 
-- Rotation
3012 
-----------------------------------------------------------------------------
3013 
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
3014 
        BEGIN
3015 
                CASE opcode(7 downto 6) IS
3016 
                        WHEN "00" =>                                    --Byte
3017 
                                                rot_rot <= OP1out(7);
3018 
                        WHEN "01"|"11" =>                               --Word
3019 
                                                rot_rot <= OP1out(15);
3020 
                        WHEN "10" =>                                    --Long
3021 
                                                rot_rot <= OP1out(31);
3022 
                        WHEN OTHERS => null;
3023 
                END CASE;
3024 
 
3025 
                CASE rot_bits IS
3026 
                        WHEN "00" =>                                    --ASL, ASR
3027 
                                                rot_lsb <= '0';
3028 
                                                rot_msb <= rot_rot;
3029 
                        WHEN "01" =>                                    --LSL, LSR
3030 
                                                rot_lsb <= '0';
3031 
                                                rot_msb <= '0';
3032 
                        WHEN "10" =>                                    --ROXL, ROXR
3033 
                                                rot_lsb <= Flags(4);
3034 
                                                rot_msb <= Flags(4);
3035 
                        WHEN "11" =>                                    --ROL, ROR
3036 
                                                rot_lsb <= rot_rot;
3037 
                                                rot_msb <= OP1out(0);
3038 
                        WHEN OTHERS => null;
3039 
                END CASE;
3040 
 
3041 
                IF rot_nop='1' THEN
3042 
                        rot_out <= OP1out;
3043 
                        rot_XC <= Flags(0);
3044 
                ELSE
3045 
                        IF opcode(8)='1' THEN           --left
3046 
                                rot_out <= OP1out(30 downto 0)&rot_lsb;
3047 
                                rot_XC <= rot_rot;
3048 
                        ELSE                                            --right
3049 
                                rot_XC <= OP1out(0);
3050 
                                rot_out <= rot_msb&OP1out(31 downto 1);
3051 
                                CASE opcode(7 downto 6) IS
3052 
                                        WHEN "00" =>                                    --Byte
3053 
                                                rot_out(7) <= rot_msb;
3054 
                                        WHEN "01"|"11" =>                               --Word
3055 
                                                rot_out(15) <= rot_msb;
3056 
                                        WHEN OTHERS =>
3057 
                                END CASE;
3058 
                        END IF;
3059 
                END IF;
3060 
        END PROCESS;
3061 
 
3062 
-----------------------------------------------------------------------------
3063 
-- MULU/MULS
3064 
-----------------------------------------------------------------------------
3065 
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
3066 
        BEGIN
3067 
                IF rising_edge(clk) THEN
3068 
                        IF clkena='1' THEN
3069 
                                IF decodeOPC='1' THEN
3070 
                                        IF opcode(8)='1' AND reg_QB(15)='1' THEN                                --MULS Neg faktor
3071 
                                                OP1sign <= '1';
3072 
                                                mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
3073 
                                        ELSE
3074 
                                                OP1sign <= '0';
3075 
                                                mulu_reg <= "0000000000000000"&reg_QB(15 downto 0);
3076 
                                        END IF;
3077 
                                ELSIF exec_MULU='1' THEN
3078 
                                        mulu_reg <= dummy_mulu;
3079 
                                END IF;
3080 
                        END IF;
3081 
                END IF;
3082 
 
3083 
                IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
3084 
                        muls_msb <= mulu_reg(31);
3085 
                ELSE
3086 
                        muls_msb <= '0';
3087 
                END IF;
3088 
 
3089 
                IF opcode(8)='1' AND OP2out(15)='1' THEN
3090 
                        sign2 <= '1';
3091 
                ELSE
3092 
                        sign2 <= '0';
3093 
                END IF;
3094 
 
3095 
                IF mulu_reg(0)='1' THEN
3096 
                        IF OP1sign='1' THEN
3097 
                                dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
3098 
                        ELSE
3099 
                                dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
3100 
                        END IF;
3101 
                ELSE
3102 
                        dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
3103 
                END IF;
3104 
        END PROCESS;
3105 
 
3106 
-----------------------------------------------------------------------------
3107 
-- DIVU
3108 
-----------------------------------------------------------------------------
3109 
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
3110 
        BEGIN
3111 
                set_V_Flag <= '0';
3112 
 
3113 
                IF rising_edge(clk) THEN
3114 
                        IF clkena='1' THEN
3115 
                                IF decodeOPC='1' THEN
3116 
                                        IF opcode(8)='1' AND reg_QB(31)='1' THEN                                -- Neg divisor
3117 
                                                div_sign <= '1';
3118 
                                                div_reg <= 0-reg_QB;
3119 
                                        ELSE
3120 
                                                div_sign <= '0';
3121 
                                                div_reg <= reg_QB;
3122 
                                        END IF;
3123 
                                ELSIF exec_DIVU='1' THEN
3124 
                                        div_reg <= div_quot;
3125 
                                END IF;
3126 
                        END IF;
3127 
                END IF;
3128 
 
3129 
                dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
3130 
 
3131 
                IF opcode(8)='1' AND OP2out(15) ='1' THEN
3132 
                        dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
3133 
                ELSE
3134 
                        dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
3135 
                END IF;
3136 
 
3137 
                IF (dummy_div_sub(16))='1' THEN
3138 
                        div_quot(31 downto 16) <= div_reg(30 downto 15);
3139 
                ELSE
3140 
                        div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
3141 
                END IF;
3142 
 
3143 
                div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
3144 
 
3145 
                IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
3146 
                        dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
3147 
                ELSE
3148 
                        dummy_div(15 downto 0) <= div_quot(15 downto 0);
3149 
                END IF;
3150 
 
3151 
                IF div_sign='1' THEN
3152 
                        dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
3153 
                ELSE
3154 
                        dummy_div(31 downto 16) <= div_quot(31 downto 16);
3155 
                END IF;
3156 
 
3157 
                IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000")       --Overflow DIVS
3158 
                        OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN        --Overflow DIVU
3159 
                        set_V_Flag <= '1';
3160 
                END IF;
3161 
        END PROCESS;
3162 
 
3163 
-----------------------------------------------------------------------------
3164 
-- Movem
3165 
-----------------------------------------------------------------------------
3166 
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
3167 
        BEGIN
3168 
                IF movem_mask(7 downto 0)="00000000" THEN
3169 
                        movem_muxa <= movem_mask(15 downto 8);
3170 
                        movem_regaddr(3) <= '1';
3171 
                ELSE
3172 
                        movem_muxa <= movem_mask(7 downto 0);
3173 
                        movem_regaddr(3) <= '0';
3174 
                END  IF;
3175 
                IF movem_muxa(3 downto 0)="0000" THEN
3176 
                        movem_muxb <= movem_muxa(7 downto 4);
3177 
                        movem_regaddr(2) <= '1';
3178 
                ELSE
3179 
                        movem_muxb <= movem_muxa(3 downto 0);
3180 
                        movem_regaddr(2) <= '0';
3181 
                END  IF;
3182 
                IF movem_muxb(1 downto 0)="00" THEN
3183 
                        movem_muxc <= movem_muxb(3 downto 2);
3184 
                        movem_regaddr(1) <= '1';
3185 
                ELSE
3186 
                        movem_muxc <= movem_muxb(1 downto 0);
3187 
                        movem_regaddr(1) <= '0';
3188 
                END  IF;
3189 
                IF movem_muxc(0)='0' THEN
3190 
                        movem_regaddr(0) <= '1';
3191 
                ELSE
3192 
                        movem_regaddr(0) <= '0';
3193 
                END  IF;
3194 
 
3195 
                movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
3196 
                                                ("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
3197 
                                                ("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
3198 
                                                ("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
3199 
 
3200 
        IF reset = '0' THEN
3201 
                        movem_busy <= '0';
3202 
                        movem_addr <= '0';
3203 
                        maskzero <= '0';
3204 
                ELSIF rising_edge(clk) THEN
3205 
                        IF clkena_in='1' AND get_movem_mask='1' THEN
3206 
                                movem_mask <= data_read(15 downto 0);
3207 
                        END IF;
3208 
                        IF clkena_in='1' AND test_maskzero='1' THEN
3209 
                                IF movem_mask=X"0000" THEN
3210 
                                        maskzero <= '1';
3211 
                                END IF;
3212 
                        END IF;
3213 
                        IF clkena_in='1' AND endOPC='1' THEN
3214 
                                maskzero <= '0';
3215 
                        END IF;
3216 
                IF clkena='1' THEN
3217 
                                IF set_movem_busy='1' THEN
3218 
                                        IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
3219 
                                                movem_busy <= '1';
3220 
                                        END IF;
3221 
                                        movem_addr <= '1';
3222 
                                END IF;
3223 
                                IF movem_addr='1' THEN
3224 
                                        CASE movem_regaddr IS
3225 
                                                WHEN "0000" => movem_mask(0)  <= '0';
3226 
                                                WHEN "0001" => movem_mask(1)  <= '0';
3227 
                                                WHEN "0010" => movem_mask(2)  <= '0';
3228 
                                                WHEN "0011" => movem_mask(3)  <= '0';
3229 
                                                WHEN "0100" => movem_mask(4)  <= '0';
3230 
                                                WHEN "0101" => movem_mask(5)  <= '0';
3231 
                                                WHEN "0110" => movem_mask(6)  <= '0';
3232 
                                                WHEN "0111" => movem_mask(7)  <= '0';
3233 
                                                WHEN "1000" => movem_mask(8)  <= '0';
3234 
                                                WHEN "1001" => movem_mask(9)  <= '0';
3235 
                                                WHEN "1010" => movem_mask(10) <= '0';
3236 
                                                WHEN "1011" => movem_mask(11) <= '0';
3237 
                                                WHEN "1100" => movem_mask(12) <= '0';
3238 
                                                WHEN "1101" => movem_mask(13) <= '0';
3239 
                                                WHEN "1110" => movem_mask(14) <= '0';
3240 
                                                WHEN "1111" => movem_mask(15) <= '0';
3241 
                                                WHEN OTHERS => null;
3242 
                                        END CASE;
3243 
                                        IF opcode(10)='1' THEN
3244 
                                                IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
3245 
                                                        movem_busy <= '0';
3246 
                                                END IF;
3247 
                                        END IF;
3248 
                                        IF movem_bits="00001" OR movem_bits="00000" THEN
3249 
                                                movem_busy <= '0';
3250 
                                                movem_addr <= '0';
3251 
                                        END IF;
3252 
                                END IF;
3253 
                        END IF;
3254 
                END IF;
3255 
        END PROCESS;
3256 
END;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.