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/**********************************************************************************
Theaia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2009  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
 
 
/*******************************************************************************
Module Description:
 
        This module defines constants that are going to be used
        all over the code. By now you have may noticed that all
        constants are pre-compilation define directives. This is
        for simulation perfomance reasons mainly.
*******************************************************************************/
 
`define THEIA_TOP uut
`define CP_TOP `THEIA_TOP.CP
`define VP_TOP `THEIA_TOP.VPX[  CVPID ].VP
 
`define CONTROL_PROCESSOR_OP_WIDTH            8
`define CONTROL_PROCESSOR_OP_NOP             `CONTROL_PROCESSOR_OP_WIDTH'd0
`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
`define CONTROL_PROCESSOR_OP_ADD             `CONTROL_PROCESSOR_OP_WIDTH'd2
`define CONTROL_PROCESSOR_OP_SUB             `CONTROL_PROCESSOR_OP_WIDTH'd3
`define CONTROL_PROCESSOR_OP_AND             `CONTROL_PROCESSOR_OP_WIDTH'd4
`define CONTROL_PROCESSOR_OP_OR              `CONTROL_PROCESSOR_OP_WIDTH'd5
`define CONTROL_PROCESSOR_OP_BRANCH          `CONTROL_PROCESSOR_OP_WIDTH'd6
`define CONTROL_PROCESSOR_OP_BEQ             `CONTROL_PROCESSOR_OP_WIDTH'd7
`define CONTROL_PROCESSOR_OP_BNE             `CONTROL_PROCESSOR_OP_WIDTH'd8
`define CONTROL_PROCESSOR_OP_BG              `CONTROL_PROCESSOR_OP_WIDTH'd9
`define CONTROL_PROCESSOR_OP_BL              `CONTROL_PROCESSOR_OP_WIDTH'd10
`define CONTROL_PROCESSOR_OP_BGE             `CONTROL_PROCESSOR_OP_WIDTH'd11
`define CONTROL_PROCESSOR_OP_BLE             `CONTROL_PROCESSOR_OP_WIDTH'd12
`define CONTROL_PROCESSOR_ASSIGN             `CONTROL_PROCESSOR_OP_WIDTH'd13
`define CONTROL_PROCESSOR_OP_COPYBLOCK       `CONTROL_PROCESSOR_OP_WIDTH'd14
`define CONTROL_PROCESSOR_OP_EXIT            `CONTROL_PROCESSOR_OP_WIDTH'd15
`define CONTROL_PROCESSOR_OP_NOT             `CONTROL_PROCESSOR_OP_WIDTH'd16
`define CONTROL_PROCESSOR_OP_SHL             `CONTROL_PROCESSOR_OP_WIDTH'd17
`define CONTROL_PROCESSOR_OP_SHR             `CONTROL_PROCESSOR_OP_WIDTH'd18
 
`define CONTROL_PROCESSOR_REG_STATUS         `CONTROL_PROCESSOR_OP_WIDTH'd2
`define CONTROL_PROCESSOR_REG_BLOCK_DST      `CONTROL_PROCESSOR_OP_WIDTH'd3
 
 
`define VPID_WIDTH                    7
`define VP_COMMAND_START_MAIN_THREAD  0
`define VP_COMMAND_STOP_MAIN_THREAD   1
 
//`define VERILATOR 1
//`define CONTROL_BUS_WIDTH                     32
`define CBC_BUS_WIDTH                     32
`define CP_MSG_ARGS_RNG                   15:0
`define CP_MSG_OPERATION_RNG              23:16
`define CP_MSG_DST_RNG                    31:24
`define CP_MSG_BCAST                      31
 
`define OMEM_SIZE                         250000
 
`define APR06 1
`define MCU_REQUEST_SIZE                      81  //32 + 32 + 8 + 8
`define MCU_FIFO_DEPTH                        8
`define MCU_COPYMEMBLOCKCMD_DSTOFF_RNG        19:0//23:0
`define MCU_COPYMEMBLOCKCMD_BLKLEN_RNG        30:20//31:24
`define MCU_COPYMEMBLOCK_TAG_BIT              31
`define MCU_COPYMEMBLOCKCMD_SRCOFF_RNG        63:32
`define MCU_COPYMEMBLOCKCMD_VPMASK_RNG        79:64
`define MCU_VPMASK_LEN                        (79-64)
//`define MCU_REQUEST_TYPE_BIT                  80           //See if it is CPBLOCKCOPY or VPCOMMAND
`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM 1'b1
`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM 1'b0
 
`define MCU_TAG_SIZE                          2
`define TAG_NULL                              2'b00
`define TAG_INSTRUCTION_ADDRESS_TYPE          2'b10
`define TAG_DATA_ADDRESS_TYPE                 2'b01
 
`define MAX_THREADS             2
`define MAX_CORES               4               //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS           2               // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS          4               //The number of memory banks for TMEM
`define MAX_TMEM_BITS           2               //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define SELECT_ALL_CORES `MAX_CORES'b1111               //XXX: Change for more cores
 
//Defnitions for the input file size (avoid nasty warnings about the size of the file being different from the
//size of the array which stores the file in verilog
`define PARAMS_ARRAY_SIZE 43            //The maximum number of byte in this input file
`define VERTEX_ARRAY_SIZE 7000          //The maximum number of byte in this input file
`define TEXTURE_BUFFER_SIZE 196608              //The maximum number of byte in this input file
//---------------------------------------------------------------------------------
//Verilog provides a `default_nettype none compiler directive.  When
//this directive is set, implicit data types are disabled, which will make any
//undeclared signal name a syntax error.This is very usefull to avoid annoying
//automatic 1 bit long wire declaration where you don't want them to be!
`default_nettype none
 
//The clock cycle
`define CLOCK_CYCLE  5
`define CLOCK_PERIOD 10
//---------------------------------------------------------------------------------
//Defines the Scale. This very important because it sets the fixed point precision.
//The Scale defines the number bits that are used as the decimal part of the number.
//The code has been written in such a way that allows you to change the value of the
//Scale, so that it is possible to experiment with different scenarios. SCALE can be
//no smaller that 1 and no bigger that WIDTH.
`define SCALE        17
 
//The next section defines the length of the registers, buses and other structures, 
//do not change this valued unless you really know what you are doing (seriously!)
`define WIDTH        32
`define WB_WIDTH     32  //width of wish-bone buses             
`define LONG_WIDTH   64
 
`define WB_SIMPLE_READ_CYCLE  0
`define WB_SIMPLE_WRITE_CYCLE 1
//---------------------------------------------------------------------------------
 
`define OPERATION_NOP    4'b0000
`define OPERATION_ADD    4'b0001
`define OPERATION_DIV    4'b0010
`define OPERATION_MUL    4'b0011
`define OPERATION_SQRT   4'b0100
`define OPERATION_LOGIC  4'b0101
`define OPERATION_IO     4'b0110
 
 
`define RS_ADD0                  4'd1   //001
`define RS_ADD1                  4'd2  //010
`define RS_DIV                   4'd3  //011
`define RS_MUL                   4'd4  //100
`define RS_SQRT                  4'd5  //101
`define RS_LOGIC                 4'd6  //110
`define RS_IO                    4'd7  //111
//----------------------------------------------------------------
//Issue bus packet structure
 
 
`define ISSUE_PACKET_SIZE 237       //The size of the packet
`define ISSUE_SRCTAG_SIZE 9
 
`define ISSUE_RSID_RNG    236:233   //4 bits
`define ISSUE_DST_RNG     232:225   //8 bits
`define ISSUE_WE_RNG      224:222   //3 bits
`define ISSUE_SCALE_OP    221
`define ISSUE_SCALER      220
`define ISSUE_SCALE0      219
`define ISSUE_SCALE1      218
`define SCALE_SIZE        4
`define ISSUE_SCALE_RNG   221:218    //4 bits
`define ISSUE_SRC1RS_RNG  217:214    //4 bits
`define ISSUE_SIGN1_RNG   213:211    //3 bits
`define ISSUE_SWZZ1_RNG   210:205    //6 bits
`define ISSUE_SRC1_DATA_RNG    204:109    //96 bits
 
`define ISSUE_SRC0RS_RNG  108:105   //4 bits
`define ISSUE_SIGN0_RNG   104:102   //3 bits
`define ISSUE_SWZZ0_RNG   101:96    //6 bits
`define ISSUE_SRC0_DATA_RNG    95:0              //96 bits
 
`define ISSUE_SRC1_TAG_RNG    213:205
`define ISSUE_SRC0_TAG_RNG    104:96
`define TAG_SIGNX 8
`define TAG_SIGNY 7
`define TAG_SIGNZ 6
`define TAG_SWLX_RNG 5:4
`define TAG_SWLY_RNG 3:2
`define TAG_SWLZ_RNG 1:0
//----------------------------------------------------------------
`define MOD_ISSUE_PACKET_SIZE     219
`define MOD_ISSUE_RSID_RNG        218:215
`define MOD_ISSUE_DST_RNG         214:207
`define MOD_ISSUE_WE_RNG          206:204
`define MOD_ISSUE_SCALE_RNG       203:200
`define MOD_ISSUE_SRC1RS_RNG      199:196
`define MOD_ISSUE_SRC1_DATA_RNG   195:100
`define MOD_ISSUE_SRC0RS_RNG      99:96
`define MOD_ISSUE_SRC0_DATA_RNG   95:0
 
 
 
`define MOD_ISSUE_TAG1_RNG        8:0
`define MOD_ISSUE_TAG0_RNG        8:0
 
`define MOD_ISSUE_SRC_SIZE 87//`DATA_ROW_WIDTH-`ISSUE_SRCTAG_SIZE
//----------------------------------------------------------------
// Commit bus packet structure
 
`define COMMIT_PACKET_SIZE 111      // The size of the packet
`define COMMIT_RSID_RNG    110:107  //4 bits
`define COMMIT_WE_RNG           106:104  //3 bits
`define COMMIT_WE_X        106
`define COMMIT_WE_Y        105
`define COMMIT_WE_Z        104
`define COMMIT_DST_RNG     103:96       //8 bits
`define COMMIT_DATA_RNG    95:0     //95 bits
`define COMMIT_X_RNG       95:64                //32 bits
`define COMMIT_Y_RNG       63:32                //32 bits
`define COMMIT_Z_RNG       31:0          //32 bits
 
`define COMMIT_SIGN_X      95
`define COMMIT_SIGN_Y      63
`define COMMIT_SIGN_Z      31
//----------------------------------------------------------------
`define MOD_COMMIT_PACKET_SIZE 114
`define MOD_SCALE_RNG          113:110
`define MOD_SIGN_RNG           109:106
`define MOD_COMMIT_TAG_RNG     109:100
`define MOD_COMMIT_SWZ_RNG     105:100
`define MOD_COMMIT_RSID_RNG    99:96
`define MOD_COMMIT_DATA_RNG    95:0     //95 bits
//----------------------------------------------------------------
`define OP_SIZE     16             //Size of the operation part of the instruction
`define OP_RNG      63:48          //Range of the operation part of the instruction
`define OP_BIT_IMM  15
//`define OP_WE_RNG   14:12
`define OP_BREAK    11
`define OP_CODE_RNG 10:0
//----------------------------------------------------------------
// Source0 structure
`define SRC0_SIZE           17
`define SRC0_RNG            16:0
`define SRC0_ADDR_SIZE      8
`define SRC0_SIGN_RNG       16:14
`define SRC0_SWZX_RNG       13:8
`define SRC0_ADDR_RNG       7:0
//----------------------------------------------------------------
// Source1 structure 
`define SRC1_SIZE           17
`define SRC1_RNG            33:17
`define SRC1_ADDR_SIZE      8
`define SRC1_SIGN_RNG       16:14
`define SRC1_SWZX_RNG       13:8
`define SRC1_ADDR_RNG       7:0
//----------------------------------------------------------------
 
`define NUMBER_OF_RSVR_STATIONS 7
 
//---------------------------------------------------------------
//Instruction structure
`define INST_IMM_RNG          31:0
`define INST_SRC0_ADDR_RNG    7:0
`define INST_SRC0_SWZL_RNG    13:8
`define INST_SRC0_SWLZ_RNG    9:8
`define INST_SRC0_SWLY_RNG    11:10
`define INST_SRC0_SWLX_RNG    13:12
`define INST_SRC0_SIGN_RNG    16:14
`define INST_SRC0_SIGNZ       14
`define INST_SRC0_SIGNY       15
`define INST_SRC0_SIGNX       16
`define INST_SCR1_ADDR_RNG    24:17
`define INST_SCR1_SWZL_RNG    30:25
`define INST_SRC1_SWLZ_RNG    26:25
`define INST_SRC1_SWLY_RNG    28:27
`define INST_SRC1_SWLX_RNG    30:29
`define INST_SRC1_SIGN_RNG    33:31
`define INST_SRC1_SIGNZ       31
`define INST_SRC1_SIGNY       32
`define INST_SRC1_SIGNX       33
`define INST_DST_RNG          41:34
`define INST_WE_Z             42
`define INST_WE_Y             43
`define INST_WE_X             44
/*
`define INST_RESERVED_RNG     46:42
*/
 
`define INST_SRC0_DISPLACED   45
`define INST_SRC1_DISPLACED   46
`define INST_DEST_ZERO        47
`define INST_ADDRMODE_RNG     47:45
`define INST_CODE_RNG         50:48
//`define INST_SCOP_RNG         53:51
`define INST_RESERVED_RNG     51:53
`define INST_BRANCH_OP_RNG    56:54
`define INST_BRANCH_BIT       57
`define INST_EOF_RNG          58           //End of flow
`define INST_SCOP_RNG         62:59
`define INST_IMM              63
 
`define INST_WE_RNG           44:42
`define SCALE_SRC1_EN  0
`define SCALE_SRC0_EN  1
`define SCALE_SRCR_EN  2
`define SCALE_OP       3
//---------------------------------------------------------------
//Compiler has to put the WE.x, WE.y and WE.z in zero (no write)
//for the branch instructions
`define BRANCH_ALWAYS               3'b000      //JMP
`define BRANCH_IF_ZERO              3'b001      //==
`define BRANCH_IF_NOT_ZERO          3'b010      //!=
`define BRANCH_IF_SIGN              3'b011      //<
`define BRANCH_IF_NOT_SIGN          3'b100      //>
`define BRANCH_IF_ZERO_OR_SIGN      3'b101              //<=
`define BRANCH_IF_ZERO_OR_NOT_SIGN  3'b110      //>=
//---------------------------------------------------------------
`define IO_OPERATION_OMWRITE 3'b0
`define IO_OPERATION_TMREAD  3'b1
 
`define SRC_RET_ADDR_RNG 95:64
`define X_RNG 95:64
`define Y_RNG 63:32
`define Z_RNG 31:0
 
 
`define ALU_BIT_ADD     0 //Bit 2 of operation is div bit
`define ALU_BIT_ASSIGN  1 //Bit 2 of operation is div bit
`define ALU_BIT_DIV     2 //Bit 2 of operation is div bit
`define ALU_BIT_MUL     3
 
 
`define OPERAND_BIT_X 15
`define OPERAND_BIT_Y 14
`define OPERAND_BIT_Z 13
 
`define NOP  `INSTRUCTION_OP_LENGTH'b0_000000000000000
`define ADD  `INSTRUCTION_OP_LENGTH'b0_000000000000001
`define AND  `INSTRUCTION_OP_LENGTH'b0_000000000000010
`define DIV  `INSTRUCTION_OP_LENGTH'b0_000000000000100
`define MUL  `INSTRUCTION_OP_LENGTH'b0_000000000001000
 
 
 
//You can play around with the size of instuctions, but keep
//in mind that Bits 3 and 4 of the Operand have a special meaning
//that is used for the jump familiy of instructions (see Documentation).
//Also the MSB of Operand is used by the decoder to distinguish 
//between Type I and Type II instructions.
 
 
`define INSTRUCTION_WIDTH       64
 
//Defines the Lenght of Memory blocks
//`define RESOURCE_VECTOR_SIZE  11
`define INSTRUCTION_ADDR_WIDTH 16
`define DATA_ROW_WIDTH        96
`define DATA_ADDRESS_WIDTH    8//7
`define ROM_ADDRESS_WIDTH     16
`define ROM_ADDRESS_SEL_MASK  `ROM_ADDRESS_WIDTH'h8000
 
 
`define SPR_CONTROL0 `DATA_ADDRESS_WIDTH'd2
`define SPR_CONTROL1 `DATA_ADDRESS_WIDTH'd3
`define SPR_TCONTROL0_MT_ENABLED              0
`define SPR_TCONTROL0_T0_INST_OFFSET_RNG      16:1
 
`define C1     `DATA_ADDRESS_WIDTH'd64
`define C2     `DATA_ADDRESS_WIDTH'd65
`define C3     `DATA_ADDRESS_WIDTH'd66
`define C4     `DATA_ADDRESS_WIDTH'd67
`define C5     `DATA_ADDRESS_WIDTH'd68
`define C6     `DATA_ADDRESS_WIDTH'd69
`define C7     `DATA_ADDRESS_WIDTH'd70
`define R1              `DATA_ADDRESS_WIDTH'd71
`define R2              `DATA_ADDRESS_WIDTH'd72
`define R3              `DATA_ADDRESS_WIDTH'd73
`define R4              `DATA_ADDRESS_WIDTH'd74
`define R5              `DATA_ADDRESS_WIDTH'd75
`define R6              `DATA_ADDRESS_WIDTH'd76
`define R7              `DATA_ADDRESS_WIDTH'd77
`define R8              `DATA_ADDRESS_WIDTH'd78
`define R9              `DATA_ADDRESS_WIDTH'd79
`define R10             `DATA_ADDRESS_WIDTH'd80
`define R11             `DATA_ADDRESS_WIDTH'd81
`define R12             `DATA_ADDRESS_WIDTH'd82
 

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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [aDefinitions.v] - Blame information for rev 230

Line No.	Rev	Author	Line
1	213	diegovalve	`/**********************************************************************************`
2			`Theaia, Ray Cast Programable graphic Processing Unit.`
3			`Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)`
4
5			`This program is free software; you can redistribute it and/or`
6			`modify it under the terms of the GNU General Public License`
7			`as published by the Free Software Foundation; either version 2`
8			`of the License, or (at your option) any later version.`
9
10			`This program is distributed in the hope that it will be useful,`
11			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`GNU General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program; if not, write to the Free Software`
17			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
18
19			`***********************************************************************************/`
20
21
22			`/*******************************************************************************`
23			`Module Description:`
24
25			`This module defines constants that are going to be used`
26			`all over the code. By now you have may noticed that all`
27			`constants are pre-compilation define directives. This is`
28			`for simulation perfomance reasons mainly.`
29			`*******************************************************************************/`
30
31			`define THEIA_TOP uut
32			`define CP_TOP `THEIA_TOP.CP
33			`define VP_TOP `THEIA_TOP.VPX[ CVPID ].VP
34
35	230	diegovalve	`define CONTROL_PROCESSOR_OP_WIDTH 8
36	213	diegovalve	`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
37			`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
38			`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
39			`define CONTROL_PROCESSOR_OP_SUB `CONTROL_PROCESSOR_OP_WIDTH'd3
40			`define CONTROL_PROCESSOR_OP_AND `CONTROL_PROCESSOR_OP_WIDTH'd4
41			`define CONTROL_PROCESSOR_OP_OR `CONTROL_PROCESSOR_OP_WIDTH'd5
42			`define CONTROL_PROCESSOR_OP_BRANCH `CONTROL_PROCESSOR_OP_WIDTH'd6
43			`define CONTROL_PROCESSOR_OP_BEQ `CONTROL_PROCESSOR_OP_WIDTH'd7
44			`define CONTROL_PROCESSOR_OP_BNE `CONTROL_PROCESSOR_OP_WIDTH'd8
45			`define CONTROL_PROCESSOR_OP_BG `CONTROL_PROCESSOR_OP_WIDTH'd9
46			`define CONTROL_PROCESSOR_OP_BL `CONTROL_PROCESSOR_OP_WIDTH'd10
47			`define CONTROL_PROCESSOR_OP_BGE `CONTROL_PROCESSOR_OP_WIDTH'd11
48			`define CONTROL_PROCESSOR_OP_BLE `CONTROL_PROCESSOR_OP_WIDTH'd12
49			`define CONTROL_PROCESSOR_ASSIGN `CONTROL_PROCESSOR_OP_WIDTH'd13
50			`define CONTROL_PROCESSOR_OP_COPYBLOCK `CONTROL_PROCESSOR_OP_WIDTH'd14
51			`define CONTROL_PROCESSOR_OP_EXIT `CONTROL_PROCESSOR_OP_WIDTH'd15
52			`define CONTROL_PROCESSOR_OP_NOT `CONTROL_PROCESSOR_OP_WIDTH'd16
53			`define CONTROL_PROCESSOR_OP_SHL `CONTROL_PROCESSOR_OP_WIDTH'd17
54			`define CONTROL_PROCESSOR_OP_SHR `CONTROL_PROCESSOR_OP_WIDTH'd18
55
56			`define CONTROL_PROCESSOR_REG_STATUS `CONTROL_PROCESSOR_OP_WIDTH'd2
57			`define CONTROL_PROCESSOR_REG_BLOCK_DST `CONTROL_PROCESSOR_OP_WIDTH'd3
58
59
60			`define VPID_WIDTH 7
61			`define VP_COMMAND_START_MAIN_THREAD 0
62			`define VP_COMMAND_STOP_MAIN_THREAD 1
63
64			//`define VERILATOR 1
65			//`define CONTROL_BUS_WIDTH 32
66			`define CBC_BUS_WIDTH 32
67			`define CP_MSG_ARGS_RNG 15:0
68			`define CP_MSG_OPERATION_RNG 23:16
69			`define CP_MSG_DST_RNG 31:24
70			`define CP_MSG_BCAST 31
71
72			`define OMEM_SIZE 250000
73
74			`define APR06 1
75			`define MCU_REQUEST_SIZE 81 //32 + 32 + 8 + 8
76			`define MCU_FIFO_DEPTH 8
77			`define MCU_COPYMEMBLOCKCMD_DSTOFF_RNG 19:0//23:0
78			`define MCU_COPYMEMBLOCKCMD_BLKLEN_RNG 30:20//31:24
79			`define MCU_COPYMEMBLOCK_TAG_BIT 31
80			`define MCU_COPYMEMBLOCKCMD_SRCOFF_RNG 63:32
81			`define MCU_COPYMEMBLOCKCMD_VPMASK_RNG 79:64
82	230	diegovalve	`define MCU_VPMASK_LEN (79-64)
83	213	diegovalve	//`define MCU_REQUEST_TYPE_BIT 80 //See if it is CPBLOCKCOPY or VPCOMMAND
84			`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM 1'b1
85			`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM 1'b0
86
87			`define MCU_TAG_SIZE 2
88			`define TAG_NULL 2'b00
89			`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b10
90			`define TAG_DATA_ADDRESS_TYPE 2'b01
91
92			`define MAX_THREADS 2
93			`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
94			`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
95			`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
96			`define MAX_TMEM_BITS 2 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
97			`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
98
99			`//Defnitions for the input file size (avoid nasty warnings about the size of the file being different from the`
100			`//size of the array which stores the file in verilog`
101			`define PARAMS_ARRAY_SIZE 43 //The maximum number of byte in this input file
102			`define VERTEX_ARRAY_SIZE 7000 //The maximum number of byte in this input file
103			`define TEXTURE_BUFFER_SIZE 196608 //The maximum number of byte in this input file
104			`//---------------------------------------------------------------------------------`
105			//Verilog provides a `default_nettype none compiler directive. When
106			`//this directive is set, implicit data types are disabled, which will make any`
107			`//undeclared signal name a syntax error.This is very usefull to avoid annoying`
108			`//automatic 1 bit long wire declaration where you don't want them to be!`
109			`default_nettype none
110
111			`//The clock cycle`
112			`define CLOCK_CYCLE 5
113			`define CLOCK_PERIOD 10
114			`//---------------------------------------------------------------------------------`
115			`//Defines the Scale. This very important because it sets the fixed point precision.`
116			`//The Scale defines the number bits that are used as the decimal part of the number.`
117			`//The code has been written in such a way that allows you to change the value of the`
118			`//Scale, so that it is possible to experiment with different scenarios. SCALE can be`
119			`//no smaller that 1 and no bigger that WIDTH.`
120			`define SCALE 17
121
122			`//The next section defines the length of the registers, buses and other structures,`
123			`//do not change this valued unless you really know what you are doing (seriously!)`
124			`define WIDTH 32
125			`define WB_WIDTH 32 //width of wish-bone buses
126			`define LONG_WIDTH 64
127
128			`define WB_SIMPLE_READ_CYCLE 0
129			`define WB_SIMPLE_WRITE_CYCLE 1
130			`//---------------------------------------------------------------------------------`
131
132			`define OPERATION_NOP 4'b0000
133			`define OPERATION_ADD 4'b0001
134			`define OPERATION_DIV 4'b0010
135			`define OPERATION_MUL 4'b0011
136			`define OPERATION_SQRT 4'b0100
137			`define OPERATION_LOGIC 4'b0101
138	230	diegovalve	`define OPERATION_IO 4'b0110
139	213	diegovalve
140
141	230	diegovalve	`define RS_ADD0 4'd1 //001
142			`define RS_ADD1 4'd2 //010
143			`define RS_DIV 4'd3 //011
144			`define RS_MUL 4'd4 //100
145			`define RS_SQRT 4'd5 //101
146			`define RS_LOGIC 4'd6 //110
147			`define RS_IO 4'd7 //111
148	213	diegovalve	`//----------------------------------------------------------------`
149			`//Issue bus packet structure`
150
151
152			`define ISSUE_PACKET_SIZE 237 //The size of the packet
153			`define ISSUE_SRCTAG_SIZE 9
154
155			`define ISSUE_RSID_RNG 236:233 //4 bits
156			`define ISSUE_DST_RNG 232:225 //8 bits
157			`define ISSUE_WE_RNG 224:222 //3 bits
158			`define ISSUE_SCALE_OP 221
159			`define ISSUE_SCALER 220
160			`define ISSUE_SCALE0 219
161			`define ISSUE_SCALE1 218
162			`define SCALE_SIZE 4
163			`define ISSUE_SCALE_RNG 221:218 //4 bits
164			`define ISSUE_SRC1RS_RNG 217:214 //4 bits
165			`define ISSUE_SIGN1_RNG 213:211 //3 bits
166			`define ISSUE_SWZZ1_RNG 210:205 //6 bits
167			`define ISSUE_SRC1_DATA_RNG 204:109 //96 bits
168
169			`define ISSUE_SRC0RS_RNG 108:105 //4 bits
170			`define ISSUE_SIGN0_RNG 104:102 //3 bits
171			`define ISSUE_SWZZ0_RNG 101:96 //6 bits
172			`define ISSUE_SRC0_DATA_RNG 95:0 //96 bits
173
174			`define ISSUE_SRC1_TAG_RNG 213:205
175			`define ISSUE_SRC0_TAG_RNG 104:96
176			`define TAG_SIGNX 8
177			`define TAG_SIGNY 7
178			`define TAG_SIGNZ 6
179			`define TAG_SWLX_RNG 5:4
180			`define TAG_SWLY_RNG 3:2
181			`define TAG_SWLZ_RNG 1:0
182			`//----------------------------------------------------------------`
183			`define MOD_ISSUE_PACKET_SIZE 219
184			`define MOD_ISSUE_RSID_RNG 218:215
185			`define MOD_ISSUE_DST_RNG 214:207
186			`define MOD_ISSUE_WE_RNG 206:204
187			`define MOD_ISSUE_SCALE_RNG 203:200
188			`define MOD_ISSUE_SRC1RS_RNG 199:196
189			`define MOD_ISSUE_SRC1_DATA_RNG 195:100
190			`define MOD_ISSUE_SRC0RS_RNG 99:96
191			`define MOD_ISSUE_SRC0_DATA_RNG 95:0
192
193	230	diegovalve
194
195	213	diegovalve	`define MOD_ISSUE_TAG1_RNG 8:0
196			`define MOD_ISSUE_TAG0_RNG 8:0
197
198			`define MOD_ISSUE_SRC_SIZE 87//`DATA_ROW_WIDTH-`ISSUE_SRCTAG_SIZE
199			`//----------------------------------------------------------------`
200			`// Commit bus packet structure`
201
202			`define COMMIT_PACKET_SIZE 111 // The size of the packet
203			`define COMMIT_RSID_RNG 110:107 //4 bits
204			`define COMMIT_WE_RNG 106:104 //3 bits
205			`define COMMIT_WE_X 106
206			`define COMMIT_WE_Y 105
207			`define COMMIT_WE_Z 104
208			`define COMMIT_DST_RNG 103:96 //8 bits
209			`define COMMIT_DATA_RNG 95:0 //95 bits
210			`define COMMIT_X_RNG 95:64 //32 bits
211			`define COMMIT_Y_RNG 63:32 //32 bits
212			`define COMMIT_Z_RNG 31:0 //32 bits
213
214			`define COMMIT_SIGN_X 95
215			`define COMMIT_SIGN_Y 63
216			`define COMMIT_SIGN_Z 31
217			`//----------------------------------------------------------------`
218			`define MOD_COMMIT_PACKET_SIZE 114
219			`define MOD_SCALE_RNG 113:110
220			`define MOD_SIGN_RNG 109:106
221			`define MOD_COMMIT_TAG_RNG 109:100
222			`define MOD_COMMIT_SWZ_RNG 105:100
223			`define MOD_COMMIT_RSID_RNG 99:96
224			`define MOD_COMMIT_DATA_RNG 95:0 //95 bits
225			`//----------------------------------------------------------------`
226			`define OP_SIZE 16 //Size of the operation part of the instruction
227			`define OP_RNG 63:48 //Range of the operation part of the instruction
228			`define OP_BIT_IMM 15
229			//`define OP_WE_RNG 14:12
230			`define OP_BREAK 11
231			`define OP_CODE_RNG 10:0
232			`//----------------------------------------------------------------`
233			`// Source0 structure`
234			`define SRC0_SIZE 17
235			`define SRC0_RNG 16:0
236			`define SRC0_ADDR_SIZE 8
237			`define SRC0_SIGN_RNG 16:14
238			`define SRC0_SWZX_RNG 13:8
239			`define SRC0_ADDR_RNG 7:0
240			`//----------------------------------------------------------------`
241			`// Source1 structure`
242			`define SRC1_SIZE 17
243			`define SRC1_RNG 33:17
244			`define SRC1_ADDR_SIZE 8
245			`define SRC1_SIGN_RNG 16:14
246			`define SRC1_SWZX_RNG 13:8
247			`define SRC1_ADDR_RNG 7:0
248			`//----------------------------------------------------------------`
249
250			`define NUMBER_OF_RSVR_STATIONS 7
251
252			`//---------------------------------------------------------------`
253			`//Instruction structure`
254			`define INST_IMM_RNG 31:0
255			`define INST_SRC0_ADDR_RNG 7:0
256			`define INST_SRC0_SWZL_RNG 13:8
257			`define INST_SRC0_SWLZ_RNG 9:8
258			`define INST_SRC0_SWLY_RNG 11:10
259			`define INST_SRC0_SWLX_RNG 13:12
260			`define INST_SRC0_SIGN_RNG 16:14
261			`define INST_SRC0_SIGNZ 14
262			`define INST_SRC0_SIGNY 15
263			`define INST_SRC0_SIGNX 16
264			`define INST_SCR1_ADDR_RNG 24:17
265			`define INST_SCR1_SWZL_RNG 30:25
266			`define INST_SRC1_SWLZ_RNG 26:25
267			`define INST_SRC1_SWLY_RNG 28:27
268			`define INST_SRC1_SWLX_RNG 30:29
269			`define INST_SRC1_SIGN_RNG 33:31
270			`define INST_SRC1_SIGNZ 31
271			`define INST_SRC1_SIGNY 32
272			`define INST_SRC1_SIGNX 33
273			`define INST_DST_RNG 41:34
274			`define INST_WE_Z 42
275			`define INST_WE_Y 43
276			`define INST_WE_X 44
277			`/*`
278			`define INST_RESERVED_RNG 46:42
279			`*/`
280
281			`define INST_SRC0_DISPLACED 45
282			`define INST_SRC1_DISPLACED 46
283			`define INST_DEST_ZERO 47
284			`define INST_ADDRMODE_RNG 47:45
285			`define INST_CODE_RNG 50:48
286			//`define INST_SCOP_RNG 53:51
287			`define INST_RESERVED_RNG 51:53
288			`define INST_BRANCH_OP_RNG 56:54
289			`define INST_BRANCH_BIT 57
290			`define INST_EOF_RNG 58 //End of flow
291			`define INST_SCOP_RNG 62:59
292			`define INST_IMM 63
293
294			`define INST_WE_RNG 44:42
295			`define SCALE_SRC1_EN 0
296			`define SCALE_SRC0_EN 1
297			`define SCALE_SRCR_EN 2
298			`define SCALE_OP 3
299			`//---------------------------------------------------------------`
300			`//Compiler has to put the WE.x, WE.y and WE.z in zero (no write)`
301			`//for the branch instructions`
302			`define BRANCH_ALWAYS 3'b000 //JMP
303			`define BRANCH_IF_ZERO 3'b001 //==
304			`define BRANCH_IF_NOT_ZERO 3'b010 //!=
305			`define BRANCH_IF_SIGN 3'b011 //<
306			`define BRANCH_IF_NOT_SIGN 3'b100 //>
307			`define BRANCH_IF_ZERO_OR_SIGN 3'b101 //<=
308			`define BRANCH_IF_ZERO_OR_NOT_SIGN 3'b110 //>=
309			`//---------------------------------------------------------------`
310	230	diegovalve	`define IO_OPERATION_OMWRITE 3'b0
311			`define IO_OPERATION_TMREAD 3'b1
312	213	diegovalve
313			`define SRC_RET_ADDR_RNG 95:64
314			`define X_RNG 95:64
315			`define Y_RNG 63:32
316			`define Z_RNG 31:0
317
318
319			`define ALU_BIT_ADD 0 //Bit 2 of operation is div bit
320			`define ALU_BIT_ASSIGN 1 //Bit 2 of operation is div bit
321			`define ALU_BIT_DIV 2 //Bit 2 of operation is div bit
322			`define ALU_BIT_MUL 3
323
324
325			`define OPERAND_BIT_X 15
326			`define OPERAND_BIT_Y 14
327			`define OPERAND_BIT_Z 13
328
329			`define NOP `INSTRUCTION_OP_LENGTH'b0_000000000000000
330			`define ADD `INSTRUCTION_OP_LENGTH'b0_000000000000001
331			`define AND `INSTRUCTION_OP_LENGTH'b0_000000000000010
332			`define DIV `INSTRUCTION_OP_LENGTH'b0_000000000000100
333			`define MUL `INSTRUCTION_OP_LENGTH'b0_000000000001000
334
335
336
337			`//You can play around with the size of instuctions, but keep`
338			`//in mind that Bits 3 and 4 of the Operand have a special meaning`
339			`//that is used for the jump familiy of instructions (see Documentation).`
340			`//Also the MSB of Operand is used by the decoder to distinguish`
341			`//between Type I and Type II instructions.`
342
343
344			`define INSTRUCTION_WIDTH 64
345
346			`//Defines the Lenght of Memory blocks`
347			//`define RESOURCE_VECTOR_SIZE 11
348			`define INSTRUCTION_ADDR_WIDTH 16
349			`define DATA_ROW_WIDTH 96
350			`define DATA_ADDRESS_WIDTH 8//7
351			`define ROM_ADDRESS_WIDTH 16
352			`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
353
354
355			`define SPR_CONTROL0 `DATA_ADDRESS_WIDTH'd2
356			`define SPR_CONTROL1 `DATA_ADDRESS_WIDTH'd3
357			`define SPR_TCONTROL0_MT_ENABLED 0
358			`define SPR_TCONTROL0_T0_INST_OFFSET_RNG 16:1
359
360			`define C1 `DATA_ADDRESS_WIDTH'd64
361			`define C2 `DATA_ADDRESS_WIDTH'd65
362			`define C3 `DATA_ADDRESS_WIDTH'd66
363			`define C4 `DATA_ADDRESS_WIDTH'd67
364			`define C5 `DATA_ADDRESS_WIDTH'd68
365			`define C6 `DATA_ADDRESS_WIDTH'd69
366			`define C7 `DATA_ADDRESS_WIDTH'd70
367			`define R1 `DATA_ADDRESS_WIDTH'd71
368			`define R2 `DATA_ADDRESS_WIDTH'd72
369			`define R3 `DATA_ADDRESS_WIDTH'd73
370			`define R4 `DATA_ADDRESS_WIDTH'd74
371			`define R5 `DATA_ADDRESS_WIDTH'd75
372			`define R6 `DATA_ADDRESS_WIDTH'd76
373			`define R7 `DATA_ADDRESS_WIDTH'd77
374			`define R8 `DATA_ADDRESS_WIDTH'd78
375			`define R9 `DATA_ADDRESS_WIDTH'd79
376			`define R10 `DATA_ADDRESS_WIDTH'd80
377			`define R11 `DATA_ADDRESS_WIDTH'd81
378			`define R12 `DATA_ADDRESS_WIDTH'd82
379