OpenCores
URL https://opencores.org/ocsvn/threeaesc/threeaesc/trunk

Subversion Repositories threeaesc

[/] [threeaesc/] [trunk/] [aes_c_1/] [scripts/] [aes_fsm_enc.do] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 entactogen 
# script general de simulacion
2 
# questa v6
3 
 
4 
vlib work
5 
 
6 
# libs
7 
 
8 
 
9 
vcom -explicit  -93 "src/aes_lib.vhd"
10 
vcom -explicit  -93 "src/dual_mem.vhd"
11 
vcom -explicit  -93 "src/aes_enc.vhd"
12 
vcom -explicit  -93 "src/aes_fsm_enc.vhd"
13 
vcom -explicit  -93 "src/tb_aes_fsm_enc.vhd"
14 
 
15 
# Sim
16 
 
17 
vsim -lib work -t 1ps tb_aes_fsm_enc
18 
 
19 
view wave
20 
view source
21 
view structure
22 
view signals
23 
add wave *
24 
 
25 
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_1
26 
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_2
27 
 
28 
mem load -infile mem/key.mem -format hex tb_aes_fsm_enc/uut/sub_keys_dram
29 
 
30 
add wave \
31 
{sim:/tb_aes_fsm_enc/uut/state }
32 
add wave \
33 
{sim:/tb_aes_fsm_enc/uut/block_out_s }
34 
add wave \
35 
{sim:/tb_aes_fsm_enc/uut/count }
36 
add wave \
37 
{sim:/tb_aes_fsm_enc/uut/key_data_1 } \
38 
{sim:/tb_aes_fsm_enc/uut/key_data_2 }
39 
add wave \
40 
{sim:/tb_aes_fsm_enc/uut/aes_round_n/sub_key }
41 
 
42 
run 10 us
43 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.