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--    This file is owned and controlled by Xilinx and must be used solely     --

--    for design, simulation, implementation and creation of design files     --

--    limited to Xilinx devices or technologies. Use with non-Xilinx          --

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--    (c) Copyright 1995-2015 Xilinx, Inc.                                    --

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--    Generated from core with identifier: xilinx.com:ip:xbip_multadd:2.0     --

--                                                                            --

--    The Xilinx LogiCORE Multiply Adder generates a multiply-add function    --

--    implemented in Xtreme DSP(TM) slices. User options allow you to         --

--    specify the wordlengths of the inputs and output.  Optimal pipelining   --

--    for maximum speed and no pipelining are available.                      --

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-- Interfaces:

--    a_intf

--    clk_intf

--    sclr_intf

--    ce_intf

--    b_intf

--    c_intf

--    pcin_intf

--    subtract_intf

--    p_intf

--    pcout_intf

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

COMPONENT InterpolateMultAdd

  PORT (

    a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);

    c : IN STD_LOGIC_VECTOR(27 DOWNTO 0);

    subtract : IN STD_LOGIC;

    p : OUT STD_LOGIC_VECTOR(27 DOWNTO 12);

    pcout : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)

  );

END COMPONENT;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : InterpolateMultAdd

  PORT MAP (

    a => a,

    b => b,

    c => c,

    subtract => subtract,

    p => p,

    pcout => pcout

  );

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file InterpolateMultAdd.vhd when simulating

-- the core, InterpolateMultAdd. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".