URL https://opencores.org/ocsvn/timerocd/timerocd/trunk

Subversion Repositories timerocd

[/] [timerocd/] [trunk/] [xilinx/] [TimerOCD/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true

Line No.	Rev	Author	Line
1	2	dewhisna	`SET busformat = BusFormatAngleBracketNotRipped`
2			`SET designentry = VHDL`
3			`SET device = xc6slx9`
4			`SET devicefamily = spartan6`
5			`SET flowvendor = Other`
6			`SET package = tqg144`
7			`SET speedgrade = -2`
8			`SET verilogsim = false`
9			`SET vhdlsim = true`

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Subversion Repositories timerocd

[/] [timerocd/] [trunk/] [xilinx/] [TimerOCD/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2