Subversion Repositories tiny_tate_bilinear_pairing

/*

 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */

`define M     503         // M is the degree of the irreducible polynomial

`define WIDTH (2*`M-1)    // width for a GF(3^M) element

`define WIDTH_D0 (1008-1)

module ram #(

    parameter DATA = 1008,

    parameter ADDR = 6

) (

    input                       clk,

    // Port A

    input   wire                a_wr,

    input   wire    [ADDR-1:0]  a_addr,

    input   wire    [DATA-1:0]  a_din,

    output  reg     [DATA-1:0]  a_dout,

    // Port B

    input   wire                b_wr,

    input   wire    [ADDR-1:0]  b_addr,

    input   wire    [DATA-1:0]  b_din,

    output  reg     [DATA-1:0]  b_dout

);

    // Shared memory

    reg [DATA-1:0] mem [(2**ADDR)-1:0];

    initial begin : init

        integer i;

        for(i = 0; i < (2**ADDR); i = i + 1)

            mem[i] = 0;

    end

    // Port A

    always @(posedge clk) begin

        a_dout      <= mem[a_addr];

        if(a_wr) begin

            a_dout      <= a_din;

            mem[a_addr] <= a_din;

        end

    end

    // Port B

    always @(posedge clk) begin

        b_dout      <= mem[b_addr];

        if(b_wr) begin

            b_dout      <= b_din;

            mem[b_addr] <= b_din;

        end

    end

endmodule