OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [bootrom.vhd] - Blame information for rev 41

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 earlz
 
2
library ieee;
3
use ieee.std_logic_1164.all;
4
use IEEE.NUMERIC_STD.ALL;
5
 
6
entity bootrom is
7
port (CLK : in std_logic;
8
      EN : in std_logic;
9
      ADDR : in std_logic_vector(4 downto 0);
10
      DATA : out std_logic_vector(15 downto 0));
11
end bootrom;
12
 
13
architecture syn of bootrom is
14
  constant ROMSIZE: integer := 64;
15 40 earlz
  type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);
16 41 earlz
  signal ROM: ROM_TYPE := (x"0801", x"0afd", x"5853", x"0600", x"1600", x"0402", x"5032", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e0c",
17
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
18 39 earlz
  signal rdata : std_logic_vector(15 downto 0);
19
begin
20
 
21
    rdata <= ROM(to_integer(unsigned(ADDR)));
22
 
23
    process (CLK)
24
    begin
25
        if (CLK'event and CLK = '1') then
26
            if (EN = '1') then
27
                DATA <= rdata;
28
            end if;
29
        end if;
30
    end process;
31
 
32
end syn;
33
 
34
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.