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These .ngc files are created by CoreGen for the following FPGA device:
 
  Xilinx xc6slx16 CSG324
 
 
To generate ip-cores for other devices, use the following cores and settings:
 
network_register:
- Core:                         Block Memory Generator
- Memory Type:                  True Dual Port RAM
- Use Byte Write Enable:        No
- Algorithm:                    Minimum Area
- Port A:
  - Write Width:                8
  - Write Depth:                64
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Port B:
  - Write Width:                32
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Optional Output Registers:    No
- Memory Initialization:        Fill with 0
- Output Reset Pins:            No
 
 
 
data_reg:
- Core:                         Block Memory Generator
- Memory Type:                  True Dual Port RAM
- Use Byte Write Enable:        No
- Algorithm:                    Minimum Area
- Port A:
  - Write Width:                8
  - Write Depth:                8192
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Port B:
  - Write Width:                32
  - Operating Mode:             Write First
  - Enable:                     Always Enabled
- Optional Output Registers:    No
- Memory Initialization:        Fill with 0
- Output Reset Pins:            No
 
 
 
async_fifo:
- Core:                         Fifo Generator
- FIFO Implementation:          Independent Clocks / Block RAM
- Read Mode:                    First-Word Fall-Through
- Data Port Parameters:
  - Write Width:                38
  - Write Depth:                128
  - Read Width:                 38
- Optional Flags:               No
- Write Port Handshaking:       No
- Read Port Handshaking:
  - Valid Flag:                 Yes / Active High
  - Underflow Flag:             No
- Initialization:
  - Reset Pin:                  Yes
  - Enable Reset Sync.:         Yes
  - Full Flags Reset Value:     0
  - Use Dout Reset:             Yes / Value: 0
  - Programmable Flags:         No
- Data Count Options:           All off

Line No.	Rev	Author	Line
1	5	sonicwave	`These .ngc files are created by CoreGen for the following FPGA device:`
2
3			`Xilinx xc6slx16 CSG324`
4
5
6			`To generate ip-cores for other devices, use the following cores and settings:`
7
8			`network_register:`
9			`- Core: Block Memory Generator`
10			`- Memory Type: True Dual Port RAM`
11			`- Use Byte Write Enable: No`
12			`- Algorithm: Minimum Area`
13			`- Port A:`
14			`- Write Width: 8`
15			`- Write Depth: 64`
16			`- Operating Mode: Write First`
17			`- Enable: Always Enabled`
18			`- Port B:`
19			`- Write Width: 32`
20			`- Operating Mode: Write First`
21			`- Enable: Always Enabled`
22			`- Optional Output Registers: No`
23			`- Memory Initialization: Fill with 0`
24			`- Output Reset Pins: No`
25
26
27
28			`data_reg:`
29			`- Core: Block Memory Generator`
30			`- Memory Type: True Dual Port RAM`
31			`- Use Byte Write Enable: No`
32			`- Algorithm: Minimum Area`
33			`- Port A:`
34			`- Write Width: 8`
35			`- Write Depth: 8192`
36			`- Operating Mode: Write First`
37			`- Enable: Always Enabled`
38			`- Port B:`
39			`- Write Width: 32`
40			`- Operating Mode: Write First`
41			`- Enable: Always Enabled`
42			`- Optional Output Registers: No`
43			`- Memory Initialization: Fill with 0`
44			`- Output Reset Pins: No`
45
46
47
48			`async_fifo:`
49			`- Core: Fifo Generator`
50			`- FIFO Implementation: Independent Clocks / Block RAM`
51			`- Read Mode: First-Word Fall-Through`
52			`- Data Port Parameters:`
53			`- Write Width: 38`
54			`- Write Depth: 128`
55			`- Read Width: 38`
56			`- Optional Flags: No`
57			`- Write Port Handshaking: No`
58			`- Read Port Handshaking:`
59			`- Valid Flag: Yes / Active High`
60			`- Underflow Flag: No`
61			`- Initialization:`
62			`- Reset Pin: Yes`
63			`- Enable Reset Sync.: Yes`
64			`- Full Flags Reset Value: 0`
65			`- Use Dout Reset: Yes / Value: 0`
66			`- Programmable Flags: No`
67			`- Data Count Options: All off`

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[/] [tosnet/] [trunk/] [gateware/] [MicroBlaze_Peripheral_rev3_2/] [pcores/] [tosnet_v3_20_a/] [netlist/] [readme_ip_xc6slx16_csg324.txt] - Blame information for rev 5