OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [baudGen.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 smuller
-----------------------------------------------------------------------------------------
2
-- baud rate generator for uart 
3
--
4
-- this module has been changed to receive the baud rate dividing counter from registers.
5
-- the two registers should be calculated as follows:
6
-- first register:
7
--              baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
8
-- second register:
9
--              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
10
--
11
-----------------------------------------------------------------------------------------
12 11 smuller
library ieee;
13
use ieee.std_logic_1164.all;
14 13 smuller
use ieee.numeric_std.all;
15 6 smuller
 
16
entity baudGen is
17
  port ( clr       : in  std_logic;                     -- global reset input
18
         clk       : in  std_logic;                     -- global clock input
19
         -- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
20
         baudFreq  : in  std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
21
         -- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
22
         baudLimit : in  std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
23
         ce16      : out std_logic);                    -- baud rate multiplyed by 16
24
end baudGen;
25
 
26
architecture Behavioral of baudGen is
27
 
28
  signal counter : std_logic_vector(15 downto 0);
29
 
30
  begin
31
    -- baud divider counter
32
    -- clock divider output
33
    process (clr, clk)
34
    begin
35
      if (clr = '1') then
36
        counter <= (others => '0');
37
        ce16 <= '0';
38
      elsif (rising_edge(clk)) then
39
        if (counter >= baudLimit) then
40 13 smuller
          counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit));
41 6 smuller
          ce16 <= '1';
42
        else
43 13 smuller
          counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq));
44 6 smuller
          ce16 <= '0';
45
        end if;
46
      end if;
47
    end process;
48
  end Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.