OpenCores
URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [uart_top.sv] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 HanySalah
//-------------------------------------------------------------------------------------------------
2 2 HanySalah
//
3 3 HanySalah
//                                     UART2BUS VERIFICATION
4 2 HanySalah
//
5 3 HanySalah
//-------------------------------------------------------------------------------------------------
6 2 HanySalah
// CREATOR    : HANY SALAH
7
// PROJECT    : UART2BUS UVM TEST BENCH
8
// UNIT       : TOP MODULE
9 3 HanySalah
//-------------------------------------------------------------------------------------------------
10
// TITLE      : UART TOP
11
// DESCRIPTION: THIS TOP MODULE THAT INHERITS THE ALL TESTBENCH COMPONENT AND CONNECT THEM TO DUT.
12
//              ALSO INCLUDES THE CLOCK GENERATION MECHANISM.
13
//-------------------------------------------------------------------------------------------------
14 2 HanySalah
// LOG DETAILS
15
//-------------
16
// VERSION      NAME        DATE        DESCRIPTION
17
//    1       HANY SALAH    11012016    FILE CREATION
18 3 HanySalah
//    2       HANY SALAH    18022016    IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
19
//-------------------------------------------------------------------------------------------------
20
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
21
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
22
//-------------------------------------------------------------------------------------------------
23 2 HanySalah
  `include "defin_lib.svh"
24
  `include "uart2bus_top.v"
25
 
26
module uart_top_tb;
27
 
28
  import uvm_pkg::*;
29
  import uart_pkg::*;
30
 
31
  `include "uvm_macros.svh"
32
 
33 3 HanySalah
  // Global System clock
34 2 HanySalah
  logic clk_glob;
35
 
36 3 HanySalah
  // UART clock (1/Baud Rate)
37 2 HanySalah
  logic clk_uart;
38
 
39 3 HanySalah
  // Glocal Asynchronous reset
40 2 HanySalah
  logic reset;
41
 
42
  assign rf_inf.int_req = arb_inf.int_req;
43
  assign rf_inf.int_gnt = arb_inf.int_gnt;
44
 
45 3 HanySalah
  // Initiate UART BFM
46 2 HanySalah
  uart_interface  uart_inf (.reset(reset),
47
                            .clock(clk_uart));
48
 
49 3 HanySalah
  // Initiate Register File BFM
50 2 HanySalah
  rf_interface    rf_inf (.reset(reset),
51
                          .clock(clk_glob));
52
 
53 3 HanySalah
  // Initiate Arbiter BFM
54 2 HanySalah
  uart_arbiter    arb_inf (.reset (reset),
55
                           .clock(clk_glob));
56
 
57 3 HanySalah
  // Initiate Design Under Test DUT
58 2 HanySalah
  uart2bus_top      dut(  .clock(clk_glob),
59
                          .reset(reset),
60
                          .ser_in(uart_inf.ser_out),
61
                          .ser_out(uart_inf.ser_in),
62
                          .int_address(rf_inf.int_address),
63
                          .int_wr_data(rf_inf.int_wr_data),
64
                          .int_write(rf_inf.int_write),
65
                          .int_rd_data(rf_inf.int_rd_data),
66
                          .int_read(rf_inf.int_read),
67
                          .int_req(arb_inf.int_req),
68
                          //.int_gnt(arb_inf.int_gnt));
69
                          .int_gnt(1'b1));
70
 
71
 
72
 
73
  initial
74
    begin
75
    reset = 1'b1;
76
    clk_glob = 1'b0;
77
    clk_uart = 1'b0;
78
    #100;
79
    reset = 1'b0;
80
    end
81
 
82 3 HanySalah
  // Clock Signals Generator
83 2 HanySalah
  initial
84
    begin
85
    fork
86
      forever
87
        begin
88
        #(`glob_clk_period/2) clk_glob = ~clk_glob;
89
        #((`glob_clk_period/2)+1) clk_glob = ~clk_glob;
90
        end
91
      forever
92
        begin
93
        #(`buad_clk_period/2) clk_uart = ~clk_uart;
94
        #((`buad_clk_period/2)+1) clk_uart = ~clk_uart;
95
        end
96
    join
97
    end
98
 
99
 
100
  initial
101
    begin
102
    uvm_config_db#(virtual uart_interface)::set(uvm_root::get(), "*", "uart_inf",uart_inf);
103
 
104
    uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
105
 
106
    uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
107
 
108 3 HanySalah
    //run_test("write_text_mode");
109 2 HanySalah
    //run_test("read_text_mode");
110
    //run_test("nop_command_mode");
111
    //run_test("read_command_mode");
112
    //run_test("write_command_mode");
113 3 HanySalah
    run_test("text_mode_test");
114 2 HanySalah
    end
115 3 HanySalah
 
116 2 HanySalah
endmodule:uart_top_tb

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.