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[/] [uart2bus_testbench/] [trunk/] [tb/] [uvm_src/] [tlm1/] [uvm_analysis_port.svh] - Blame information for rev 16

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1 16 HanySalah
//
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//----------------------------------------------------------------------
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//   Copyright 2007-2011 Mentor Graphics Corporation
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//   Copyright 2007-2011 Cadence Design Systems, Inc.
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//   Copyright 2010 Synopsys, Inc.
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//   All Rights Reserved Worldwide
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//
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//   Licensed under the Apache License, Version 2.0 (the
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//   "License"); you may not use this file except in
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//   compliance with the License.  You may obtain a copy of
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//   the License at
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//
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//       http://www.apache.org/licenses/LICENSE-2.0
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//
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//   Unless required by applicable law or agreed to in
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//   writing, software distributed under the License is
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//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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//   CONDITIONS OF ANY KIND, either express or implied.  See
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//   the License for the specific language governing
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//   permissions and limitations under the License.
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//----------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Title: Analysis Ports
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//------------------------------------------------------------------------------
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//
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// This section defines the port, export, and imp classes used for transaction
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// analysis.
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//
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Class: uvm_analysis_port
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//
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// Broadcasts a value to all subscribers implementing a .
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//
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//| class mon extends uvm_component;
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//|   uvm_analysis_port#(trans) ap;
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//|
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//|   function new(string name = "sb", uvm_component parent = null);
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//|      super.new(name, parent);
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//|      ap = new("ap", this);
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//|   endfunction
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//|
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//|   task run_phase(uvm_phase phase);
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//|       trans t;
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//|       ...
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//|       ap.write(t);
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//|       ...
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//|   endfunction
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//| endclass
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//------------------------------------------------------------------------------
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class uvm_analysis_port # (type T = int)
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  extends uvm_port_base # (uvm_tlm_if_base #(T,T));
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  function new (string name, uvm_component parent);
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    super.new (name, parent, UVM_PORT, 0, UVM_UNBOUNDED_CONNECTIONS);
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    m_if_mask = `UVM_TLM_ANALYSIS_MASK;
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  endfunction
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  virtual function string get_type_name();
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    return "uvm_analysis_port";
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  endfunction
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  // Method: write
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  // Send specified value to all connected interface
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  function void write (input T t);
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    uvm_tlm_if_base # (T, T) tif;
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    for (int i = 0; i < this.size(); i++) begin
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      tif = this.get_if (i);
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      if ( tif == null )
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        uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE);
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      tif.write (t);
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    end
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  endfunction
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endclass
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//------------------------------------------------------------------------------
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// Class: uvm_analysis_imp
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//
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// Receives all transactions broadcasted by a . It serves as
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// the termination point of an analysis port/export/imp connection. The component
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// attached to the ~imp~ class--called a ~subscriber~-- implements the analysis
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// interface.
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//
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// Will invoke the ~write(T)~ method in the parent component.
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// The implementation of the ~write(T)~ method must not modify
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// the value passed to it.
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//
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//| class sb extends uvm_component;
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//|   uvm_analysis_imp#(trans, sb) ap;
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//|
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//|   function new(string name = "sb", uvm_component parent = null);
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//|      super.new(name, parent);
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//|      ap = new("ap", this);
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//|   endfunction
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//|
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//|   function void write(trans t);
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//|       ...
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//|   endfunction
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//| endclass
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//------------------------------------------------------------------------------
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class uvm_analysis_imp #(type T=int, type IMP=int)
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  extends uvm_port_base #(uvm_tlm_if_base #(T,T));
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  `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,"uvm_analysis_imp",IMP)
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  function void write (input T t);
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    m_imp.write (t);
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  endfunction
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endclass
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//------------------------------------------------------------------------------
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// Class: uvm_analysis_export
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//
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// Exports a lower-level  to its parent.
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//------------------------------------------------------------------------------
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class uvm_analysis_export #(type T=int)
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  extends uvm_port_base #(uvm_tlm_if_base #(T,T));
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  // Function: new
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  // Instantiate the export.
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  function new (string name, uvm_component parent = null);
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    super.new (name, parent, UVM_EXPORT, 1, UVM_UNBOUNDED_CONNECTIONS);
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    m_if_mask = `UVM_TLM_ANALYSIS_MASK;
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  endfunction
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  virtual function string get_type_name();
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    return "uvm_analysis_export";
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  endfunction
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  // analysis port differs from other ports in that it broadcasts
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  // to all connected interfaces. Ports only send to the interface
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  // at the index specified in a call to set_if (0 by default).
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  function void write (input T t);
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    uvm_tlm_if_base #(T, T) tif;
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    for (int i = 0; i < this.size(); i++) begin
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      tif = this.get_if (i);
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      if (tif == null)
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         uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE);
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      tif.write (t);
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    end
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  endfunction
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endclass
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