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<br/>
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<tr><td colspan="2"><h2><a name="Processes"></a>
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Processes</h2></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#ae6956df8a9f0a3de7db54c4ad6fe3299">CLK_I_process</a>&#160;</td><td class="memItemRight" valign="bottom"><b> (  )</b></td></tr>
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Components</h2></td></tr>
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<tr class="memdesc:a5c22d67786c8d4257bb37aa2efb6f261"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset Input.  <a href="#a5c22d67786c8d4257bb37aa2efb6f261"></a><br/></td></tr>
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<tr><td colspan="2"><h2><a name="Constants"></a>
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Constants</h2></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a">RST_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:a6ee791bdb5df4ccca9dd8a946696dd8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7">CLK_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:a4c7b3772ac2a67a7c972f606d2cc4ec7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<tr class="memdesc:a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77">DAT_I0</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">others</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">&gt;</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:a4b087814632daf135cbc38c252bbaf77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a7c70578f707dad097203747f4870b498">WE_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a861b1f4580110b89b3be07a9a2b29bf7">STB_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a15d41e2405387248c782af0ee1e11517">serial_in</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">:</span><span class="vhdlchar">=</span><span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">'</span><span class="vhdlchar"> </span></b></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#aa444d95093cb5f8197bb92d21da1f43a">DAT_O0</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:aa444d95093cb5f8197bb92d21da1f43a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4">ACK_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:a21f50c72e4e45c54ea44e014934312d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a30dda061cfa67e7c4d84ec0f5d1cb295">serial_out</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
169 
<tr class="memdesc:a30dda061cfa67e7c4d84ec0f5d1cb295"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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<a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a051f773441045ed070bde8d6139dd817">data_Avaible</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
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<tr class="memdesc:a051f773441045ed070bde8d6139dd817"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal to connect with UUT. <br/></td></tr>
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</table>
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<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
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<div class="textblock">
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<p>Definition at line <a class="el" href="test_uart__wishbone__slave_8vhd_source.html#l00013">13</a> of file <a class="el" href="test_uart__wishbone__slave_8vhd_source.html">testUart_wishbone_slave.vhd</a>.</p>
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</div><hr/><h2>Member Data Documentation</h2>
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<a class="anchor" id="a5c22d67786c8d4257bb37aa2efb6f261"></a>
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<div class="memitem">
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<div class="memproto">
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      <table class="memname">
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        <tr>
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          <td class="memname"><a class="el" href="classtest_uart__wishbone__slave_1_1behavior.html#a5c22d67786c8d4257bb37aa2efb6f261">uart_wishbone_slave</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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        </tr>
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      </table>
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</div>
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<div class="memdoc">
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<p>Reset Input. </p>
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<p>Clock Input Address input Data Input 0 Data Output 0 Write enable input Strobe input (Works like a chip select) Ack output Uart serial input Flag to indicate data avaible </p>
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<p>Definition at line <a class="el" href="test_uart__wishbone__slave_8vhd_source.html#l00017">17</a> of file <a class="el" href="test_uart__wishbone__slave_8vhd_source.html">testUart_wishbone_slave.vhd</a>.</p>
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</div>
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</div>
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<hr/>The documentation for this class was generated from the following files:<ul>
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<li>E:/uart_block/hdl/iseProject/<a class="el" href="test_uart__wishbone__slave_8vhd_source.html">testUart_wishbone_slave.vhd</a></li>
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</ul>
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</div><!-- contents -->
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</div>
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    <ul>
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      <li class="navelem"><a class="el" href="classtest_uart__wishbone__slave.html">testUart_wishbone_slave</a>      </li>
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