Subversion Repositories uart_block

\section{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R Entity Reference}

\label{class_s_e_r_i_a_l_m_a_s_t_e_r}\index{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R@{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}}

Inheritance diagram for S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R\-:\begin{figure}[H]

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\includegraphics[height=2.000000cm]{class_s_e_r_i_a_l_m_a_s_t_e_r}

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\end{figure}

\subsection*{Entities}

\begin{DoxyCompactItemize}

\item

{\bf Behavioral} architecture

\begin{DoxyCompactList}\small\item\em Test the \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave}. \end{DoxyCompactList}\end{DoxyCompactItemize}

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\subsection*{Use Clauses}

 \begin{DoxyCompactItemize}

\item

{\bf pkg\-Definitions}   \label{class_s_e_r_i_a_l_m_a_s_t_e_r_ac442dca664056131bdaf5c92e4351e01}

\begin{DoxyCompactList}\small\item\em Use C\-P\-U Definitions package. \end{DoxyCompactList}\end{DoxyCompactItemize}

\subsection*{Ports}

 \begin{DoxyCompactItemize}

\item

{\bf A\-C\-K\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_a69bf28b7e6429b3f3e35bee455901578}

\begin{DoxyCompactList}\small\item\em Ack input. \end{DoxyCompactList}\item

{\bf A\-D\-R\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (   1    downto    0  ) } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_a2331d71c69b0b20c1901627667a01471}

\begin{DoxyCompactList}\small\item\em Address output. \end{DoxyCompactList}\item

{\bf C\-L\-K\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_a3582288d52a135a76a7de24d94b4dc68}

\begin{DoxyCompactList}\small\item\em Clock input. \end{DoxyCompactList}\item

{\bf C\-Y\-C\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_af4b285f68ab4fa480bd6095c34ff5135}

\begin{DoxyCompactList}\small\item\em Cycle output. \end{DoxyCompactList}\item

{\bf D\-A\-T\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  ) } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_ab94f6b71e9a7ec24dab537723d8345d2}

\begin{DoxyCompactList}\small\item\em Data input. \end{DoxyCompactList}\item

{\bf D\-A\-T\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  ) } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_a6b78f3634fd733feea1e7504e6a4ddc4}

\begin{DoxyCompactList}\small\item\em Data output. \end{DoxyCompactList}\item

{\bf R\-S\-T\-\_\-\-I}  {\bfseries {\bfseries in }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_ae9849e01c32648d8e13000bd5fb9760f}

\begin{DoxyCompactList}\small\item\em Reset input. \end{DoxyCompactList}\item

{\bf S\-E\-L\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_abd694a1729387db79033dcfd6bf320bc}

\begin{DoxyCompactList}\small\item\em Select output. \end{DoxyCompactList}\item

{\bf S\-T\-B\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_ac7ffa7be9c863895b0f1d1ec6e101169}

\begin{DoxyCompactList}\small\item\em Strobe output (Works like a chip select) \end{DoxyCompactList}\item

{\bf W\-E\-\_\-\-O}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_a41e7e86f235d5f673607008142e1ecad}

\begin{DoxyCompactList}\small\item\em Write enable. \end{DoxyCompactList}\item

{\bf byte\-\_\-rec}  {\bfseries {\bfseries out }} {\bfseries std\-\_\-logic\-\_\-vector (   7    downto    0  ) } \label{class_s_e_r_i_a_l_m_a_s_t_e_r_af163828b322f105b0c03724feea898ce}

\begin{DoxyCompactList}\small\item\em Signal byte received (Used to debug on the out leds) \end{DoxyCompactList}\end{DoxyCompactItemize}

\subsection{Detailed Description}

Definition at line 11 of file S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R.\-vhd.

The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}

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E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R.\-vhd}\end{DoxyCompactItemize}