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1 40 leonardoar 
\section{behavior Architecture Reference}
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\label{classtest_uart__wishbone__slave_1_1behavior}\index{behavior@{behavior}}
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\\*
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\\*
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\subsection*{Processes}
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 \begin{DoxyCompactItemize}
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\item
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{\bf C\-L\-K\-\_\-\-I\-\_\-process}{\bfseries  (  )}\label{classtest_uart__wishbone__slave_1_1behavior_ae6956df8a9f0a3de7db54c4ad6fe3299}
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\item
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{\bf stim\-\_\-proc}{\bfseries  (  )}\label{classtest_uart__wishbone__slave_1_1behavior_ad2efa6785cff833c341e27596b21aeb5}
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\end{DoxyCompactItemize}
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\subsection*{Components}
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 \begin{DoxyCompactItemize}
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\item
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{\bf uart\-\_\-wishbone\-\_\-slave}  {\bfseries }
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\begin{DoxyCompactList}\small\item\em Reset Input. \end{DoxyCompactList}\end{DoxyCompactItemize}
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\subsection*{Constants}
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 \begin{DoxyCompactItemize}
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\item
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{\bf C\-L\-K\-\_\-\-I\-\_\-period} {\bfseries time  \-:=  20  ns } \label{classtest_uart__wishbone__slave_1_1behavior_aaba2bb0049306c18f246a63f6bc9c712}
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\end{DoxyCompactItemize}
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\subsection*{Signals}
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 \begin{DoxyCompactItemize}
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\item
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{\bf R\-S\-T\-\_\-\-I} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_uart__wishbone__slave_1_1behavior_a6ee791bdb5df4ccca9dd8a946696dd8a}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf C\-L\-K\-\_\-\-I} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_uart__wishbone__slave_1_1behavior_a4c7b3772ac2a67a7c972f606d2cc4ec7}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf A\-D\-R\-\_\-\-I0} {\bfseries std\-\_\-logic\-\_\-vector (   1    downto    0  )  \-:= (  others  = $>$ '  0  '  ) } \label{classtest_uart__wishbone__slave_1_1behavior_a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf D\-A\-T\-\_\-\-I0} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  )  \-:= (  others  = $>$ '  0  '  ) } \label{classtest_uart__wishbone__slave_1_1behavior_a4b087814632daf135cbc38c252bbaf77}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf W\-E\-\_\-\-I} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_uart__wishbone__slave_1_1behavior_a7c70578f707dad097203747f4870b498}
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\item
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{\bf S\-T\-B\-\_\-\-I} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_uart__wishbone__slave_1_1behavior_a861b1f4580110b89b3be07a9a2b29bf7}
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\item
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{\bf serial\-\_\-in} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_uart__wishbone__slave_1_1behavior_a15d41e2405387248c782af0ee1e11517}
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\item
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{\bf D\-A\-T\-\_\-\-O0} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  ) } \label{classtest_uart__wishbone__slave_1_1behavior_aa444d95093cb5f8197bb92d21da1f43a}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf A\-C\-K\-\_\-\-O} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a21f50c72e4e45c54ea44e014934312d4}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf serial\-\_\-out} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a30dda061cfa67e7c4d84ec0f5d1cb295}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item
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{\bf data\-\_\-\-Avaible} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a051f773441045ed070bde8d6139dd817}
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\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\end{DoxyCompactItemize}
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\subsection{Detailed Description}
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Definition at line 13 of file test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd.
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\subsection{Member Data Documentation}
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\index{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior@{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior}!uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}}
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\index{uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}!testUart_wishbone_slave::behavior@{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior}}
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\subsubsection[{uart\-\_\-wishbone\-\_\-slave}]{\setlength{\rightskip}{0pt plus 5cm}{\bf uart\-\_\-wishbone\-\_\-slave} {\bfseries  } \hspace{0.3cm}{\ttfamily  [Component]}}\label{classtest_uart__wishbone__slave_1_1behavior_a5c22d67786c8d4257bb37aa2efb6f261}
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Reset Input.
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Clock Input Address input Data Input 0 Data Output 0 Write enable input Strobe input (Works like a chip select) Ack output Uart serial input Flag to indicate data avaible
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Definition at line 17 of file test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd.
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The documentation for this class was generated from the following files\-:\begin{DoxyCompactItemize}
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\item
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E\-:/uart\-\_\-block/hdl/ise\-Project/test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd\end{DoxyCompactItemize}

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