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[/] [uart_fiber/] [trunk/] [Version4/] [main.vhd] - Blame information for rev 21

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
--use IEEE.NUMERIC_STD.ALL;
 
 
entity main is
    Port ( iCLK : in  STD_LOGIC;
           RX : out  STD_LOGIC;
           TX : in  STD_LOGIC;
           optic_out : out  STD_LOGIC;
           optic_in : in  STD_LOGIC;
 
                          setting : in  STD_LOGIC_VECTOR(1 downto 0)
 
 
                          );
end main;
 
architecture Behavioral of main is
 
 
 
 
COMPONENT TX_to_spdif
        PORT(
                iCLK : IN std_logic;
                TX : IN std_logic;
                OPTIC_OUT : OUT std_logic;
                period01 : in STD_LOGIC_VECTOR(6 downto 0);
                periodA : in STD_LOGIC_VECTOR(6 downto 0);
                period10 : in STD_LOGIC_VECTOR(6 downto 0);
                period : in STD_LOGIC_VECTOR(6 downto 0);
                baud_div : in STD_LOGIC_VECTOR(6 downto 0);
                direct_mode : in STD_LOGIC
 
 
                );
        END COMPONENT;
COMPONENT spdif_to_RX
        PORT(
                iCLK : IN std_logic;
                OPTIC_IN : IN std_logic;
                RX : OUT std_logic;
 
                periodA : in STD_LOGIC_VECTOR(6 downto 0);
                period10 : in STD_LOGIC_VECTOR(6 downto 0)
 
 
 
                );
        END COMPONENT;
 
 
COMPONENT q_period is
    PORT ( period : in  STD_LOGIC_VECTOR (6 downto 0);
           period01 : out  STD_LOGIC_VECTOR (6 downto 0);
           periodA : out  STD_LOGIC_VECTOR (6 downto 0);
           period10 : out  STD_LOGIC_VECTOR (6 downto 0)
                          );
END COMPONENT;
 
 
signal period01 :STD_LOGIC_VECTOR(6 downto 0);
signal periodA :STD_LOGIC_VECTOR(6 downto 0);
signal period10 :STD_LOGIC_VECTOR(6 downto 0);
 
signal period : STD_LOGIC_VECTOR(6 downto 0);
signal baud_div : STD_LOGIC_VECTOR(6 downto 0);
signal direct_mode : STD_LOGIC;
 
 
 
 
begin
 
process(setting)
 
begin
 
        if(setting(1 downto 0)="00")then--2.0Mb/s @ 50Mhz
        --period<=('0','0','1','1','0','0','1');--25
        period<=('0','0','1','0','1','0','0');--20
        --period<=('0','1','1','0','0','1','0');--50
        baud_div<=(0=>'1',others=>'0');--1
        direct_mode<='0';
        elsif(setting(1 downto 0)="01")then--1.25Mb/s
        period<=('0','0','1','0','1','0','0');--20
        baud_div<=(1=>'1',others=>'0');--2
        direct_mode<='0';
        else--115207 b/s
        period<=('0','0','1','0','1','0','0');--20
        baud_div<=(0=>'1',others=>'0');--1
        direct_mode<='1';
        --period<=('0','1','1','1','1','1','0');--62
        --baud_div<=('0','0','0','0','1','1','1');--7
        end if;
 
end process;
 
 
 
 
 
q_period_inst:q_period
 Port map (period=>period,
                                period01=>period01,
                                periodA=>periodA,
                                period10=>period10
                                );
 
TX_to_spdif_inst:TX_to_spdif
    Port map ( iCLK=> iCLK,
              TX => TX,
                                  optic_out => optic_out,
                                  period01=>period01,
                                  periodA=>periodA,
                                  period10=>period10,
                                  period=>period,
                                  baud_div=>baud_div,
                                  direct_mode=>direct_mode
                                  );
spdif_to_RX_inst:spdif_to_RX
    Port map ( iCLK=>iCLK,
                                        optic_in => optic_in,
                                        RX => RX,
                                        periodA=>periodA,
                                        period10=>period10
 
 
                                  );
 
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	21	chipmaker7
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.ALL;`
4
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.std_logic_unsigned.all;`
7			`--use IEEE.NUMERIC_STD.ALL;`
8
9
10			`entity main is`
11			`Port ( iCLK : in STD_LOGIC;`
12			`RX : out STD_LOGIC;`
13			`TX : in STD_LOGIC;`
14			`optic_out : out STD_LOGIC;`
15			`optic_in : in STD_LOGIC;`
16
17			`setting : in STD_LOGIC_VECTOR(1 downto 0)`
18
19
20			`);`
21			`end main;`
22
23			`architecture Behavioral of main is`
24
25
26
27
28			`COMPONENT TX_to_spdif`
29			`PORT(`
30			`iCLK : IN std_logic;`
31			`TX : IN std_logic;`
32			`OPTIC_OUT : OUT std_logic;`
33			`period01 : in STD_LOGIC_VECTOR(6 downto 0);`
34			`periodA : in STD_LOGIC_VECTOR(6 downto 0);`
35			`period10 : in STD_LOGIC_VECTOR(6 downto 0);`
36			`period : in STD_LOGIC_VECTOR(6 downto 0);`
37			`baud_div : in STD_LOGIC_VECTOR(6 downto 0);`
38			`direct_mode : in STD_LOGIC`
39
40
41			`);`
42			`END COMPONENT;`
43			`COMPONENT spdif_to_RX`
44			`PORT(`
45			`iCLK : IN std_logic;`
46			`OPTIC_IN : IN std_logic;`
47			`RX : OUT std_logic;`
48
49			`periodA : in STD_LOGIC_VECTOR(6 downto 0);`
50			`period10 : in STD_LOGIC_VECTOR(6 downto 0)`
51
52
53
54			`);`
55			`END COMPONENT;`
56
57
58			`COMPONENT q_period is`
59			`PORT ( period : in STD_LOGIC_VECTOR (6 downto 0);`
60			`period01 : out STD_LOGIC_VECTOR (6 downto 0);`
61			`periodA : out STD_LOGIC_VECTOR (6 downto 0);`
62			`period10 : out STD_LOGIC_VECTOR (6 downto 0)`
63			`);`
64			`END COMPONENT;`
65
66
67			`signal period01 :STD_LOGIC_VECTOR(6 downto 0);`
68			`signal periodA :STD_LOGIC_VECTOR(6 downto 0);`
69			`signal period10 :STD_LOGIC_VECTOR(6 downto 0);`
70
71			`signal period : STD_LOGIC_VECTOR(6 downto 0);`
72			`signal baud_div : STD_LOGIC_VECTOR(6 downto 0);`
73			`signal direct_mode : STD_LOGIC;`
74
75
76
77
78			`begin`
79
80			`process(setting)`
81
82			`begin`
83
84			`if(setting(1 downto 0)="00")then--2.0Mb/s @ 50Mhz`
85			`--period<=('0','0','1','1','0','0','1');--25`
86			`period<=('0','0','1','0','1','0','0');--20`
87			`--period<=('0','1','1','0','0','1','0');--50`
88			`baud_div<=(0=>'1',others=>'0');--1`
89			`direct_mode<='0';`
90			`elsif(setting(1 downto 0)="01")then--1.25Mb/s`
91			`period<=('0','0','1','0','1','0','0');--20`
92			`baud_div<=(1=>'1',others=>'0');--2`
93			`direct_mode<='0';`
94			`else--115207 b/s`
95			`period<=('0','0','1','0','1','0','0');--20`
96			`baud_div<=(0=>'1',others=>'0');--1`
97			`direct_mode<='1';`
98			`--period<=('0','1','1','1','1','1','0');--62`
99			`--baud_div<=('0','0','0','0','1','1','1');--7`
100			`end if;`
101
102			`end process;`
103
104
105
106
107
108			`q_period_inst:q_period`
109			`Port map (period=>period,`
110			`period01=>period01,`
111			`periodA=>periodA,`
112			`period10=>period10`
113			`);`
114
115			`TX_to_spdif_inst:TX_to_spdif`
116			`Port map ( iCLK=> iCLK,`
117			`TX => TX,`
118			`optic_out => optic_out,`
119			`period01=>period01,`
120			`periodA=>periodA,`
121			`period10=>period10,`
122			`period=>period,`
123			`baud_div=>baud_div,`
124			`direct_mode=>direct_mode`
125			`);`
126			`spdif_to_RX_inst:spdif_to_RX`
127			`Port map ( iCLK=>iCLK,`
128			`optic_in => optic_in,`
129			`RX => RX,`
130			`periodA=>periodA,`
131			`period10=>period10`
132
133
134			`);`
135
136
137
138			`end Behavioral;`
139

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[/] [uart_fiber/] [trunk/] [Version4/] [main.vhd] - Blame information for rev 21