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ultra_embe |
### USB Peripheral Interface
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Github: [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/usb_device)
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This component is a simple USB Peripheral Interface (Device) implementation with an AXI4-Lite slave register interface, and
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with a UTMI interface for connection to a USB PHY.
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It has been designed to support USB2.0, but currently has been only tested in Full Speed peripheral mode (12Mbit/s).
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##### Features
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* USB 2.0 Device mode support.
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* Simple register data read/write interface (low performance / not DMA based).
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* UTMI PHY interface (see my UTMI to ULPI Conversion wrapper project to allow connection to a ULPI PHY e.g. USB3300)
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* Current build configuration has 4 endpoints
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##### Limitations
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* Only tested for USB-FS (Full Speed / 12Mbit/s) only.
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* AXI4-L address and data must arrive in the same cycle.
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##### Software
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Provided with a USB-CDC test stack (USB Serial port) with loopback/echo example.
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To make this functional on your platform;
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* Set USB_DEV_BASE to the correct address for the peripheral.
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* Implement the millisecond timer functions in timer.h.
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* Change USB_BYTE_SWAP16 in usbf_defs.h if your CPU is big endian.
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##### Testing
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Verified under simulation then tested on FPGA as a USB-CDC mode peripheral (USB serial port) against Linux & Windows PCs.
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##### References
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* [USB 2.0 Specification](https://usb.org/developers/docs/usb20_docs)
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* [UTMI Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf)
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* [USB Made Simple](http://www.usbmadesimple.co.uk/)
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* [UTMI to ULPI Conversion](https://github.com/ultraembedded/cores/tree/master/ulpi_wrapper)
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##### Register Map
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| Offset | Name | Description |
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| ------ | ---- | ------------- |
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| 0x00 | USB_FUNC_CTRL | [RW] Control Register |
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| 0x04 | USB_FUNC_STAT | [RW] Status Register |
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| 0x08 | USB_FUNC_ADDR | [RW] Address Register |
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| 0x0c | USB_EP0_CFG | [RW] Endpoint 0 Configuration |
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| 0x10 | USB_EP0_TX_CTRL | [RW] Endpoint 0 Tx Control |
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| 0x14 | USB_EP0_RX_CTRL | [W] Endpoint 0 Rx Control |
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| 0x18 | USB_EP0_STS | [R] Endpoint 0 status |
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| 0x1c | USB_EP0_DATA | [RW] Endpoint Data FIFO |
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| 0x20 | USB_EP1_CFG | [RW] Endpoint 1 Configuration |
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| 0x24 | USB_EP1_TX_CTRL | [RW] Endpoint 1 Tx Control |
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| 0x28 | USB_EP1_RX_CTRL | [W] Endpoint 1 Rx Control |
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| 0x2c | USB_EP1_STS | [R] Endpoint 1 status |
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| 0x30 | USB_EP1_DATA | [RW] Endpoint Data FIFO |
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| 0x34 | USB_EP2_CFG | [RW] Endpoint 2 Configuration |
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| 0x38 | USB_EP2_TX_CTRL | [RW] Endpoint 2 Tx Control |
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| 0x3c | USB_EP2_RX_CTRL | [W] Endpoint 2 Rx Control |
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| 0x40 | USB_EP2_STS | [R] Endpoint 2 status |
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| 0x44 | USB_EP2_DATA | [RW] Endpoint Data FIFO |
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| 0x48 | USB_EP3_CFG | [RW] Endpoint 3 Configuration |
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| 0x4c | USB_EP3_TX_CTRL | [RW] Endpoint 3 Tx Control |
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| 0x50 | USB_EP3_RX_CTRL | [W] Endpoint 3 Rx Control |
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| 0x54 | USB_EP3_STS | [R] Endpoint 3 status |
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| 0x58 | USB_EP3_DATA | [RW] Endpoint Data FIFO |
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##### Register: USB_FUNC_CTRL
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 8 | HS_CHIRP_EN | High-speed Chirp Enable |
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| 7 | PHY_DMPULLDOWN | UTMI PHY D+ Pulldown Enable |
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| 6 | PHY_DPPULLDOWN | UTMI PHY D+ Pulldown Enable |
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| 5 | PHY_TERMSELECT | UTMI PHY Termination Select |
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| 4:3 | PHY_XCVRSELECT | UTMI PHY Transceiver Select |
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| 2:1 | PHY_OPMODE | UTMI PHY Output Mode |
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| 0 | INT_EN_SOF | Interrupt enable - SOF reception |
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##### Register: USB_FUNC_STAT
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 13 | RST | USB Reset Detected (cleared on write) |
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| 12:11 | LINESTATE | USB line state (bit 1 = D+, bit 0 = D-) |
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| 10:0 | FRAME | Frame number |
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##### Register: USB_FUNC_ADDR
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 6:0 | DEV_ADDR | Device address |
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##### Register: USB_EPx_CFG
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 3 | INT_RX | Interrupt on Rx ready |
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| 2 | INT_TX | Interrupt on Tx complete |
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| 1 | STALL_EP | Stall endpoint |
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| 0 | ISO | Isochronous endpoint |
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##### Register: USB_EPx_TX_CTRL
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 17 | TX_FLUSH | Invalidate Tx buffer |
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| 16 | TX_START | Transmit start - enable transmit of endpoint data |
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| 10:0 | TX_LEN | Transmit length |
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##### Register: USB_EPx_RX_CTRL
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 1 | RX_FLUSH | Invalidate Rx buffer |
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| 0 | RX_ACCEPT | Receive data accepted (read) |
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##### Register: USB_EPx_STS
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 20 | TX_ERR | Transmit error (buffer underrun) |
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| 19 | TX_BUSY | Transmit busy (active) |
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| 18 | RX_ERR | Receive error - CRC mismatch or buffer overflow |
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| 17 | RX_SETUP | SETUP request received |
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| 16 | RX_READY | Receive ready (data available) |
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| 10:0 | RX_COUNT | Endpoint received length (RD) |
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##### Register: USB_EPx_DATA
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| Bits | Name | Description |
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| ---- | ---- | -------------- |
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| 7:0 | DATA | Read or write from Rx or Tx endpoint FIFO |
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