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Subversion Repositories usb_fpga_2_04

[/] [usb_fpga_2_04/] [trunk/] [include/] [ztex-fpga4.h] - Blame information for rev 2

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/*!
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
   Copyright (C) 2009-2014 ZTEX GmbH.
   http://www.ztex.de
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
/*
    FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)
*/
 
#ifndef[ZTEX_FPGA_H]
#define[ZTEX_FPGA_H]
 
#define[@CAPABILITY_FPGA;]
 
__xdata BYTE fpga_checksum;         // checksum
__xdata DWORD fpga_bytes;           // transfered bytes
__xdata BYTE fpga_init_b;           // init_b state (should be 222 after configuration)
__xdata BYTE fpga_flash_result;     // result of automatic fpga configuarion from Flash
 
/* *********************************************************************
   ***** reset_fpga ****************************************************
   ********************************************************************* */
static void reset_fpga_int (BYTE mode) {                // reset FPGA
    unsigned short k;
    IFCONFIG = bmBIT7;
    SYNCDELAY;
    PORTACFG = 0;
    PORTCCFG = 0;
    OEC &= ~( bmBIT1 | bmBIT2);  // in: DOUT, INIT_B
//  out:  RESET,   M1,      CCLK,    M0,      CSI
    OEA = bmBIT1 | bmBIT2 | bmBIT4 | bmBIT5 | bmBIT7;
    IOA = bmBIT7 | bmBIT4 | mode;
    OEC |= bmBIT3;              // out: RDWR_B
    IOC &= ~bmBIT3;
    wait(10);
 
    IOA = bmBIT1 | mode;                                // ready for configuration
    k=0;
    while (!IOC2 && k<65535)
        k++;
 
    fpga_init_b = IOC2 ? 200 : 100;
    fpga_bytes = 0;
    fpga_checksum = 0;
}
 
static void reset_fpga () {
    reset_fpga_int(bmBIT2);
}
 
static void reset_fpga_flash () {
    reset_fpga_int(bmBIT2 | bmBIT4 | bmBIT5 );
}
 
/* *********************************************************************
   ***** init_fpga_configuration ***************************************
   ********************************************************************* */
static void init_fpga_configuration () {
    {
        PRE_FPGA_RESET
    }
    reset_fpga();                       // reset FPGA
}
 
/* *********************************************************************
   ***** post_fpga_confog **********************************************
   ********************************************************************* */
static void post_fpga_config () {
    POST_FPGA_CONFIG
}
 
/* *********************************************************************
   ***** finish_fpga_configuration *************************************
   ********************************************************************* */
static void finish_fpga_configuration () {
    BYTE w;
    fpga_init_b += IOC2 ? 22 : 11;
 
    for ( w=0; w<64; w++ ) {
        IOA4 = 1; IOA4 = 0;
    }
    IOA7 = 1;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
    IOA4 = 1; IOA4 = 0;
 
    OEA = 0;
    OEC &= ~bmBIT3;
    if ( IOA1 )  {
        IOA1 = 1;
        post_fpga_config();
    }
 
    IOA1 = 1;
    OEA |= bmBIT1;
}
 
 
/* *********************************************************************
   ***** EP0 vendor request 0x30 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x30,,          // get FPGA state
    MEM_COPY1(fpga_checksum,EP0BUF+1,7);
    OEA &= ~bmBIT1;
    if ( IOA1 )  {
        EP0BUF[0] = 0;                    // FPGA configured 
        IOA1 = 1;
        OEA |= bmBIT1;
    }
    else {
        EP0BUF[0] = 1;                   // FPGA unconfigured 
        reset_fpga();                   // prepare FPGA for configuration
    }
    EP0BUF[8] = 1;                      // bit order for bitstream in Flash memory: swapped
 
    EP0BCH = 0;
    EP0BCL = 9;
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x31 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));;  // reset FPGA
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x32 ***************************************
   ********************************************************************* */
void fpga_send_ep0() {                  // send FPGA configuration data
    BYTE oOEB;
    oOEB = OEB;
    OEB = 255;
    fpga_bytes += ep0_payload_transfer;
    __asm
        mov     dptr,#_EP0BCL
        movx    a,@dptr
        jz      010000$
        mov     r2,a
        mov     _AUTOPTRL1,#(_EP0BUF)
        mov     _AUTOPTRH1,#(_EP0BUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_fpga_checksum
        movx    a,@dptr
        mov     r1,a
        mov     dptr,#_XAUTODAT1
010001$:
        movx    a,@dptr                 // 2
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        add     a,r1                    // 1
        mov     r1,a                    // 1
        clr     _IOA4                   // 2
        djnz    r2, 010001$             // 4
 
        mov     dptr,#_fpga_checksum
        mov     a,r1
        movx    @dptr,a
 
010000$:
        __endasm;
    OEB = oOEB;
    if ( EP0BCL<64 ) {
        finish_fpga_configuration();
    }
}
 
ADD_EP0_VENDOR_COMMAND((0x32,,          // send FPGA configuration data
,,
    fpga_send_ep0();
));;
 
 
#ifdef[HS_FPGA_CONF_EP]
 
#ifeq[HS_FPGA_CONF_EP][2]
#elifeq[HS_FPGA_CONF_EP][4]
#elifeq[HS_FPGA_CONF_EP][6]
#elifneq[HS_FPGA_CONF_EP][8]
#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
#endif
 
#define[@CAPABILITY_HS_FPGA;]
 
/* *********************************************************************
   ***** EP0 vendor request 0x33 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_REQUEST((0x33,,          // get high speed fpga configuration endpoint and interface 
    EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
    EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
    EP0BCH = 0;
    EP0BCL = 2;
,,));;
 
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
/* *********************************************************************
   ***** interrupt routine for EPn *************************************
   ********************************************************************* */
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
 
static void fpga_hs_send_isr () __interrupt {
    BYTE oOEB;
    oOEB = OEB;
 
    EUSB = 0;                    // block all USB interrupts
 
    fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) | EPHS_FPGA_CONF_EPBCL;
 
    OEB = 255;
    __asm
        mov     dptr,#_EPHS_FPGA_CONF_EPBCL
        movx    a,@dptr
        mov     r2,a
        anl     a,#7
        mov     r3,a
        mov     dptr,#_EPHS_FPGA_CONF_EPBCH
        movx    a,@dptr
        addc    a,#0
 
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     a,r1
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     a,r1
        rrc     a
        mov     r1,a
        mov     a,r2
        rrc     a
        mov     r2,a
 
        mov     _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)
        mov     _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)
        mov     _AUTOPTRSETUP,#0x07
        mov     dptr,#_XAUTODAT1
 
        mov     a,r3
        jz      010011$
010012$:
        movx    a,@dptr                 // 2, 1
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
        djnz    r3, 010012$             // 4
 
 
        mov     a,r2
        jz      010010$
010011$:
        movx    a,@dptr                 // 2, 1
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 2
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 3
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 4
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 5
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 6
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 7
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        movx    a,@dptr                 // 2, 8
        mov     _IOB,a                  // 2
        setb    _IOA4                   // 2
        clr     _IOA4                   // 2
 
        djnz    r2, 010011$             // 4
 
010010$:
        __endasm;
    OEB = oOEB;
 
 
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
//    EPHS_FPGA_CONF_EPBCL = 0x80;      // skip package, (re)arm EP
    SYNCDELAY;
 
    EXIF &= ~bmBIT4;
    EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
 
    EUSB = 1;
}
#endif
 
/* *********************************************************************
   ***** EP0 vendor command 0x34 ***************************************
   ********************************************************************* */
// FIFO write wave form
const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
{
/* LenBr */ 0x01,     0x88,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
/* Opcode*/ 0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x02,     0x00,
/* Output*/ 0x04,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x04, // CTL2 <-> 0x04
/* LFun  */ 0x00,     0x36,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
};
 
const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
{
/* LenBr */ 0x02,     0x01,     0x90,     0x01,     0x01,     0x01,     0x01,     0x07,
/* Opcode*/ 0x02,     0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x00,
/* Output*/ 0x04,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x04,  // CTL2 <-> 0x04
/* LFun  */ 0x00,     0x00,     0x36,     0x00,     0x00,     0x00,     0x00,     0x3F,
};
 
 
void init_cpld_fpga_configuration() {
    IFCONFIG = bmBIT7 | bmBIT6 | 2;     // Internal source, 48MHz, GPIF
 
    GPIFREADYCFG = 0;
    GPIFCTLCFG = 0x0;
    GPIFIDLECS = 0;
    GPIFIDLECTL = 4;
    GPIFWFSELECT = 0x4E;
    GPIFREADYSTAT = 0;
 
    MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
 
    FLOWSTATE = 0;
    FLOWLOGIC = 0x10;
    FLOWEQ0CTL = 0;
    FLOWEQ1CTL = 0;
    FLOWHOLDOFF = 0;
    FLOWSTB = 0;
    FLOWSTBEDGE = 0;
    FLOWSTBHPERIOD = 0;
 
    REVCTL = 0x1;                               // reset fifo
    SYNCDELAY;
    FIFORESET = 0x80;
    SYNCDELAY;
    FIFORESET = HS_FPGA_CONF_EP;
    SYNCDELAY;
    FIFORESET = 0x0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPFIFOCFG = 0;                // config fifo
    SYNCDELAY;
    EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
    SYNCDELAY;
    EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
    SYNCDELAY;
 
    GPIFTCB3 = 1;                               // abort after at least 14*65536 transactions
    SYNCDELAY;
    GPIFTCB2 = 0;
    SYNCDELAY;
    GPIFTCB1 = 0;
    SYNCDELAY;
    GPIFTCB0 = 0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPGPIFTRIG = 0xff;           // arm fifos
    SYNCDELAY;
 
    OEA &= ~bmBIT4;                             // disable CCLK output
    OEA |= bmBIT0;                              // enable GPIF mode of CPLD
    IOA0 = 0;
}
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;
 
void init_epn_fpga_configuration() {
 
    IFCONFIG = bmBIT7;
 
    REVCTL = 0x03;                              // reset fifo
    SYNCDELAY;
    FIFORESET = 0x80;
    SYNCDELAY;
    FIFORESET = HS_FPGA_CONF_EP;
    SYNCDELAY;
    FIFORESET = 0x0;
    SYNCDELAY;
 
    EPHS_FPGA_CONF_EPFIFOCFG = 0;                // config fifo
    SYNCDELAY;
 
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
    OUTPKTEND = 0x8HS_FPGA_CONF_EP;     // skip package, (re)arm EP
    SYNCDELAY;
 
/*    EPHS_FPGA_CONF_EPBCL = 0x80;      // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY;
    EPHS_FPGA_CONF_EPBCL = 0x80;        // skip package, (re)arm EP
    SYNCDELAY; */
 
    old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;
    old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;
    INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;
    INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);
 
    EXIF &= ~bmBIT4;
    EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);
}
#endif
 
ADD_EP0_VENDOR_COMMAND((0x34,,                  // init fpga configuration
    init_fpga_configuration();
 
    EPHS_FPGA_CONF_EPCS &= ~bmBIT0;             // clear stall bit
 
    GPIFABORT = 0xFF;                           // abort pendig 
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
    if ( is_ufm_1_15x )
        init_epn_fpga_configuration();
    else
#endif    
        init_cpld_fpga_configuration();
 
,,));;
 
 
/* *********************************************************************
   ***** EP0 vendor command 0x35 ***************************************
   ********************************************************************* */
ADD_EP0_VENDOR_COMMAND((0x35,,          // finish fpga configuration
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
    if ( is_ufm_1_15x ) {
        INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;
        INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;
    }
    else
#endif    
    {
        IOA0 = 1;                           // disable GPIF mode of CPLD
        IOA4 = 1;                           // enable CCLK output
        OEA |= bmBIT4;
 
        GPIFABORT = 0xFF;
        SYNCDELAY;
        IFCONFIG &= 0xf0;
        SYNCDELAY;
 
    }
    finish_fpga_configuration();
,,));;
 
#endif  // HS_FPGA_CONF_EP
 
 
 
#ifeq[FLASH_BITSTREAM_ENABLED][1]
#ifeq[FLASH_ENABLED][1]
 
/* *********************************************************************
   ***** fpga_send_bitstream_from_flash ********************************
   ********************************************************************* */
void fpga_send_bitstream_from_flash (WORD size) {
        size;                   // this avoids stupid warnings
__asm
        push    _OEB
 
        mov     r5,dpl          // = size
        mov     r6,dph
 
        // fpga_bytes+=size
        mov     dptr,#_fpga_bytes
        movx    a,@dptr
        mov     r1,a
        inc     dptr
        movx    a,@dptr
        mov     r2,a
        inc     dptr
        movx    a,@dptr
        mov     r3,a
        inc     dptr
        movx    a,@dptr
        mov     r4,a
 
        mov     dptr,#_fpga_bytes
        mov     a,r5
        add     a,r1
        movx    @dptr,a
        mov     a,r6
        addc    a,r2
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r3
        inc     dptr
        movx    @dptr,a
        mov     a,#0
        addc    a,r4
        inc     dptr
        movx    @dptr,a
 
// size == 512
        cjne    r5,#0,010004$   
        cjne    r6,#2,010004$   
//      sjmp    010004$ 
 
        mov     _OEB, #0
        anl     _OEA, #(~bmBIT4)        
        setb    _IOC6
        anl     _OEC, #(~bmBIT6)
        orl     _OEA, #(bmBIT3)
        clr     _IOA3
        setb    _IOA3
        anl     _OEA, #(~bmBIT3)
 
        mov     r2, #3                  // wait > 2 clocks
010008$:
        mov     r1, #227
010009$:
        djnz    r1, 010009$
        djnz    r2, 010008$
 
        setb    _IOA4
        orl     _OEA, #(bmBIT4) 
        orl     _OEC, #(bmBIT6)
        clr     _IOC6
        pop     _OEB
        ret
 
// size != 512
010004$:
        mov     _OEB,#1
010003$:
        cjne    r5,#0x00,010002$        // 4
        cjne    r6,#0x00,010002$
        pop     _OEB
        ret
010002$:                                // approx 105 cycles per byte
        mov     C, _IOC4  // 2
        mov     _IOB0, C  // 2
        clr     _IOA4     // 2
        setb    _IOA4     // 2
        setb    _IOC6     // 2
        clr     _IOC6     // 2
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        mov     C, _IOC4
        mov     _IOB0, C
        clr     _IOA4
        setb    _IOA4
        setb    _IOC6
        clr     _IOC6
 
        dec     r5                      // 1
        cjne    r5,#0xff,010003$        // 4
        dec     r6
        sjmp    010003$
__endasm;
}
 
#include[ztex-fpga-flash1.h]
 
#else
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
#define[FLASH_BITSTREAM_ENABLED][0]
#endif
#endif
 
#endif  /*ZTEX_FPGA_H*/

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Subversion Repositories usb_fpga_2_04

[/] [usb_fpga_2_04/] [trunk/] [include/] [ztex-fpga4.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`/*!`
2			`ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers`
3			`Copyright (C) 2009-2014 ZTEX GmbH.`
4			`http://www.ztex.de`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License version 3 as`
8			`published by the Free Software Foundation.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program; if not, see http://www.gnu.org/licenses/.`
17			`!*/`
18
19			`/*`
20			`FPGA support for ZTEX USB FPGA Modules 1.15 (not 1.15y)`
21			`*/`
22
23			`#ifndef[ZTEX_FPGA_H]`
24			`#define[ZTEX_FPGA_H]`
25
26			`#define[@CAPABILITY_FPGA;]`
27
28			`__xdata BYTE fpga_checksum; // checksum`
29			`__xdata DWORD fpga_bytes; // transfered bytes`
30			`__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)`
31			`__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash`
32
33			`/* *********************************************************************`
34			`*** reset_fpga **************************************************`
35			`********************************************************************* */`
36			`static void reset_fpga_int (BYTE mode) { // reset FPGA`
37			`unsigned short k;`
38			`IFCONFIG = bmBIT7;`
39			`SYNCDELAY;`
40			`PORTACFG = 0;`
41			`PORTCCFG = 0;`
42			`OEC &= ~( bmBIT1 \| bmBIT2); // in: DOUT, INIT_B`
43			`// out: RESET, M1, CCLK, M0, CSI`
44			`OEA = bmBIT1 \| bmBIT2 \| bmBIT4 \| bmBIT5 \| bmBIT7;`
45			`IOA = bmBIT7 \| bmBIT4 \| mode;`
46			`OEC \|= bmBIT3; // out: RDWR_B`
47			`IOC &= ~bmBIT3;`
48			`wait(10);`
49
50			`IOA = bmBIT1 \| mode; // ready for configuration`
51			`k=0;`
52			`while (!IOC2 && k<65535)`
53			`k++;`
54
55			`fpga_init_b = IOC2 ? 200 : 100;`
56			`fpga_bytes = 0;`
57			`fpga_checksum = 0;`
58			`}`
59
60			`static void reset_fpga () {`
61			`reset_fpga_int(bmBIT2);`
62			`}`
63
64			`static void reset_fpga_flash () {`
65			`reset_fpga_int(bmBIT2 \| bmBIT4 \| bmBIT5 );`
66			`}`
67
68			`/* *********************************************************************`
69			`*** init_fpga_configuration *************************************`
70			`********************************************************************* */`
71			`static void init_fpga_configuration () {`
72			`{`
73			`PRE_FPGA_RESET`
74			`}`
75			`reset_fpga(); // reset FPGA`
76			`}`
77
78			`/* *********************************************************************`
79			`*** post_fpga_confog ********************************************`
80			`********************************************************************* */`
81			`static void post_fpga_config () {`
82			`POST_FPGA_CONFIG`
83			`}`
84
85			`/* *********************************************************************`
86			`*** finish_fpga_configuration ***********************************`
87			`********************************************************************* */`
88			`static void finish_fpga_configuration () {`
89			`BYTE w;`
90			`fpga_init_b += IOC2 ? 22 : 11;`
91
92			`for ( w=0; w<64; w++ ) {`
93			`IOA4 = 1; IOA4 = 0;`
94			`}`
95			`IOA7 = 1;`
96			`IOA4 = 1; IOA4 = 0;`
97			`IOA4 = 1; IOA4 = 0;`
98			`IOA4 = 1; IOA4 = 0;`
99			`IOA4 = 1; IOA4 = 0;`
100
101			`OEA = 0;`
102			`OEC &= ~bmBIT3;`
103			`if ( IOA1 ) {`
104			`IOA1 = 1;`
105			`post_fpga_config();`
106			`}`
107
108			`IOA1 = 1;`
109			`OEA \|= bmBIT1;`
110			`}`
111
112
113			`/* *********************************************************************`
114			`*** EP0 vendor request 0x30 *************************************`
115			`********************************************************************* */`
116			`ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state`
117			`MEM_COPY1(fpga_checksum,EP0BUF+1,7);`
118			`OEA &= ~bmBIT1;`
119			`if ( IOA1 ) {`
120			`EP0BUF[0] = 0; // FPGA configured`
121			`IOA1 = 1;`
122			`OEA \|= bmBIT1;`
123			`}`
124			`else {`
125			`EP0BUF[0] = 1; // FPGA unconfigured`
126			`reset_fpga(); // prepare FPGA for configuration`
127			`}`
128			`EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped`
129
130			`EP0BCH = 0;`
131			`EP0BCL = 9;`
132			`,,));;`
133
134
135			`/* *********************************************************************`
136			`*** EP0 vendor command 0x31 *************************************`
137			`********************************************************************* */`
138			`ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));; // reset FPGA`
139
140
141			`/* *********************************************************************`
142			`*** EP0 vendor command 0x32 *************************************`
143			`********************************************************************* */`
144			`void fpga_send_ep0() { // send FPGA configuration data`
145			`BYTE oOEB;`
146			`oOEB = OEB;`
147			`OEB = 255;`
148			`fpga_bytes += ep0_payload_transfer;`
149			`__asm`
150			`mov dptr,#_EP0BCL`
151			`movx a,@dptr`
152			`jz 010000$`
153			`mov r2,a`
154			`mov _AUTOPTRL1,#(_EP0BUF)`
155			`mov _AUTOPTRH1,#(_EP0BUF >> 8)`
156			`mov _AUTOPTRSETUP,#0x07`
157			`mov dptr,#_fpga_checksum`
158			`movx a,@dptr`
159			`mov r1,a`
160			`mov dptr,#_XAUTODAT1`
161			`010001$:`
162			`movx a,@dptr // 2`
163			`mov _IOB,a // 2`
164			`setb _IOA4 // 2`
165			`add a,r1 // 1`
166			`mov r1,a // 1`
167			`clr _IOA4 // 2`
168			`djnz r2, 010001$ // 4`
169
170			`mov dptr,#_fpga_checksum`
171			`mov a,r1`
172			`movx @dptr,a`
173
174			`010000$:`
175			`__endasm;`
176			`OEB = oOEB;`
177			`if ( EP0BCL<64 ) {`
178			`finish_fpga_configuration();`
179			`}`
180			`}`
181
182			`ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data`
183			`,,`
184			`fpga_send_ep0();`
185			`));;`
186
187
188			`#ifdef[HS_FPGA_CONF_EP]`
189
190			`#ifeq[HS_FPGA_CONF_EP][2]`
191			`#elifeq[HS_FPGA_CONF_EP][4]`
192			`#elifeq[HS_FPGA_CONF_EP][6]`
193			`#elifneq[HS_FPGA_CONF_EP][8]`
194			#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
195			`#endif`
196
197			`#define[@CAPABILITY_HS_FPGA;]`
198
199			`/* *********************************************************************`
200			`*** EP0 vendor request 0x33 *************************************`
201			`********************************************************************* */`
202			`ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface`
203			`EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint`
204			`EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface`
205			`EP0BCH = 0;`
206			`EP0BCL = 2;`
207			`,,));;`
208
209
210			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
211			`/* *********************************************************************`
212			`*** interrupt routine for EPn ***********************************`
213			`********************************************************************* */`
214			`xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;`
215
216			`static void fpga_hs_send_isr () __interrupt {`
217			`BYTE oOEB;`
218			`oOEB = OEB;`
219
220			`EUSB = 0; // block all USB interrupts`
221
222			`fpga_bytes += (EPHS_FPGA_CONF_EPBCH<<8) \| EPHS_FPGA_CONF_EPBCL;`
223
224			`OEB = 255;`
225			`__asm`
226			`mov dptr,#_EPHS_FPGA_CONF_EPBCL`
227			`movx a,@dptr`
228			`mov r2,a`
229			`anl a,#7`
230			`mov r3,a`
231			`mov dptr,#_EPHS_FPGA_CONF_EPBCH`
232			`movx a,@dptr`
233			`addc a,#0`
234
235			`rrc a`
236			`mov r1,a`
237			`mov a,r2`
238			`rrc a`
239			`mov r2,a`
240
241			`mov a,r1`
242			`rrc a`
243			`mov r1,a`
244			`mov a,r2`
245			`rrc a`
246			`mov r2,a`
247
248			`mov a,r1`
249			`rrc a`
250			`mov r1,a`
251			`mov a,r2`
252			`rrc a`
253			`mov r2,a`
254
255			`mov _AUTOPTRL1,#(_EPHS_FPGA_CONF_EPFIFOBUF)`
256			`mov _AUTOPTRH1,#(_EPHS_FPGA_CONF_EPFIFOBUF >> 8)`
257			`mov _AUTOPTRSETUP,#0x07`
258			`mov dptr,#_XAUTODAT1`
259
260			`mov a,r3`
261			`jz 010011$`
262			`010012$:`
263			`movx a,@dptr // 2, 1`
264			`mov _IOB,a // 2`
265			`setb _IOA4 // 2`
266			`clr _IOA4 // 2`
267			`djnz r3, 010012$ // 4`
268
269
270			`mov a,r2`
271			`jz 010010$`
272			`010011$:`
273			`movx a,@dptr // 2, 1`
274			`mov _IOB,a // 2`
275			`setb _IOA4 // 2`
276			`clr _IOA4 // 2`
277
278			`movx a,@dptr // 2, 2`
279			`mov _IOB,a // 2`
280			`setb _IOA4 // 2`
281			`clr _IOA4 // 2`
282
283			`movx a,@dptr // 2, 3`
284			`mov _IOB,a // 2`
285			`setb _IOA4 // 2`
286			`clr _IOA4 // 2`
287
288			`movx a,@dptr // 2, 4`
289			`mov _IOB,a // 2`
290			`setb _IOA4 // 2`
291			`clr _IOA4 // 2`
292
293			`movx a,@dptr // 2, 5`
294			`mov _IOB,a // 2`
295			`setb _IOA4 // 2`
296			`clr _IOA4 // 2`
297
298			`movx a,@dptr // 2, 6`
299			`mov _IOB,a // 2`
300			`setb _IOA4 // 2`
301			`clr _IOA4 // 2`
302
303			`movx a,@dptr // 2, 7`
304			`mov _IOB,a // 2`
305			`setb _IOA4 // 2`
306			`clr _IOA4 // 2`
307
308			`movx a,@dptr // 2, 8`
309			`mov _IOB,a // 2`
310			`setb _IOA4 // 2`
311			`clr _IOA4 // 2`
312
313			`djnz r2, 010011$ // 4`
314
315			`010010$:`
316			`__endasm;`
317			`OEB = oOEB;`
318
319
320			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
321			`// EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
322			`SYNCDELAY;`
323
324			`EXIF &= ~bmBIT4;`
325			`EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);`
326
327			`EUSB = 1;`
328			`}`
329			`#endif`
330
331			`/* *********************************************************************`
332			`*** EP0 vendor command 0x34 *************************************`
333			`********************************************************************* */`
334			`// FIFO write wave form`
335			`const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =`
336			`{`
337			`/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,`
338			`/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,`
339			`/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04`
340			`/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,`
341			`};`
342
343			`const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =`
344			`{`
345			`/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,`
346			`/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,`
347			`/* Output*/ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, // CTL2 <-> 0x04`
348			`/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,`
349			`};`
350
351
352			`void init_cpld_fpga_configuration() {`
353			`IFCONFIG = bmBIT7 \| bmBIT6 \| 2; // Internal source, 48MHz, GPIF`
354
355			`GPIFREADYCFG = 0;`
356			`GPIFCTLCFG = 0x0;`
357			`GPIFIDLECS = 0;`
358			`GPIFIDLECTL = 4;`
359			`GPIFWFSELECT = 0x4E;`
360			`GPIFREADYSTAT = 0;`
361
362			`MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);`
363
364			`FLOWSTATE = 0;`
365			`FLOWLOGIC = 0x10;`
366			`FLOWEQ0CTL = 0;`
367			`FLOWEQ1CTL = 0;`
368			`FLOWHOLDOFF = 0;`
369			`FLOWSTB = 0;`
370			`FLOWSTBEDGE = 0;`
371			`FLOWSTBHPERIOD = 0;`
372
373			`REVCTL = 0x1; // reset fifo`
374			`SYNCDELAY;`
375			`FIFORESET = 0x80;`
376			`SYNCDELAY;`
377			`FIFORESET = HS_FPGA_CONF_EP;`
378			`SYNCDELAY;`
379			`FIFORESET = 0x0;`
380			`SYNCDELAY;`
381
382			`EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo`
383			`SYNCDELAY;`
384			`EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 \| 0;`
385			`SYNCDELAY;`
386			`EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;`
387			`SYNCDELAY;`
388
389			`GPIFTCB3 = 1; // abort after at least 14*65536 transactions`
390			`SYNCDELAY;`
391			`GPIFTCB2 = 0;`
392			`SYNCDELAY;`
393			`GPIFTCB1 = 0;`
394			`SYNCDELAY;`
395			`GPIFTCB0 = 0;`
396			`SYNCDELAY;`
397
398			`EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos`
399			`SYNCDELAY;`
400
401			`OEA &= ~bmBIT4; // disable CCLK output`
402			`OEA \|= bmBIT0; // enable GPIF mode of CPLD`
403			`IOA0 = 0;`
404			`}`
405
406			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
407			`xdata WORD old_hsconf_intvec_h, old_hsconf_intvec_l;`
408
409			`void init_epn_fpga_configuration() {`
410
411			`IFCONFIG = bmBIT7;`
412
413			`REVCTL = 0x03; // reset fifo`
414			`SYNCDELAY;`
415			`FIFORESET = 0x80;`
416			`SYNCDELAY;`
417			`FIFORESET = HS_FPGA_CONF_EP;`
418			`SYNCDELAY;`
419			`FIFORESET = 0x0;`
420			`SYNCDELAY;`
421
422			`EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo`
423			`SYNCDELAY;`
424
425			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
426			`SYNCDELAY;`
427			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
428			`SYNCDELAY;`
429			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
430			`SYNCDELAY;`
431			`OUTPKTEND = 0x8HS_FPGA_CONF_EP; // skip package, (re)arm EP`
432			`SYNCDELAY;`
433
434			`/* EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
435			`SYNCDELAY;`
436			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
437			`SYNCDELAY;`
438			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
439			`SYNCDELAY;`
440			`EPHS_FPGA_CONF_EPBCL = 0x80; // skip package, (re)arm EP`
441			`SYNCDELAY; */`
442
443			`old_hsconf_intvec_l = INTVEC_EPHS_FPGA_CONF_EP.addrL;`
444			`old_hsconf_intvec_h = INTVEC_EPHS_FPGA_CONF_EP.addrH;`
445			`INTVEC_EPHS_FPGA_CONF_EP.addrH=((unsigned short)(&fpga_hs_send_isr)) >> 8;`
446			`INTVEC_EPHS_FPGA_CONF_EP.addrL=(unsigned short)(&fpga_hs_send_isr);`
447
448			`EXIF &= ~bmBIT4;`
449			`EPIRQ = 1 << ((HS_FPGA_CONF_EP >> 1)+3);`
450			`}`
451			`#endif`
452
453			`ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration`
454			`init_fpga_configuration();`
455
456			`EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit`
457
458			`GPIFABORT = 0xFF; // abort pendig`
459
460			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
461			`if ( is_ufm_1_15x )`
462			`init_epn_fpga_configuration();`
463			`else`
464			`#endif`
465			`init_cpld_fpga_configuration();`
466
467			`,,));;`
468
469
470			`/* *********************************************************************`
471			`*** EP0 vendor command 0x35 *************************************`
472			`********************************************************************* */`
473			`ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration`
474			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
475			`if ( is_ufm_1_15x ) {`
476			`INTVEC_EPHS_FPGA_CONF_EP.addrL = old_hsconf_intvec_l;`
477			`INTVEC_EPHS_FPGA_CONF_EP.addrH = old_hsconf_intvec_h;`
478			`}`
479			`else`
480			`#endif`
481			`{`
482			`IOA0 = 1; // disable GPIF mode of CPLD`
483			`IOA4 = 1; // enable CCLK output`
484			`OEA \|= bmBIT4;`
485
486			`GPIFABORT = 0xFF;`
487			`SYNCDELAY;`
488			`IFCONFIG &= 0xf0;`
489			`SYNCDELAY;`
490
491			`}`
492			`finish_fpga_configuration();`
493			`,,));;`
494
495			`#endif // HS_FPGA_CONF_EP`
496
497
498
499			`#ifeq[FLASH_BITSTREAM_ENABLED][1]`
500			`#ifeq[FLASH_ENABLED][1]`
501
502			`/* *********************************************************************`
503			`*** fpga_send_bitstream_from_flash ******************************`
504			`********************************************************************* */`
505			`void fpga_send_bitstream_from_flash (WORD size) {`
506			`size; // this avoids stupid warnings`
507			`__asm`
508			`push _OEB`
509
510			`mov r5,dpl // = size`
511			`mov r6,dph`
512
513			`// fpga_bytes+=size`
514			`mov dptr,#_fpga_bytes`
515			`movx a,@dptr`
516			`mov r1,a`
517			`inc dptr`
518			`movx a,@dptr`
519			`mov r2,a`
520			`inc dptr`
521			`movx a,@dptr`
522			`mov r3,a`
523			`inc dptr`
524			`movx a,@dptr`
525			`mov r4,a`
526
527			`mov dptr,#_fpga_bytes`
528			`mov a,r5`
529			`add a,r1`
530			`movx @dptr,a`
531			`mov a,r6`
532			`addc a,r2`
533			`inc dptr`
534			`movx @dptr,a`
535			`mov a,#0`
536			`addc a,r3`
537			`inc dptr`
538			`movx @dptr,a`
539			`mov a,#0`
540			`addc a,r4`
541			`inc dptr`
542			`movx @dptr,a`
543
544			`// size == 512`
545			`cjne r5,#0,010004$`
546			`cjne r6,#2,010004$`
547			`// sjmp 010004$`
548
549			`mov _OEB, #0`
550			`anl _OEA, #(~bmBIT4)`
551			`setb _IOC6`
552			`anl _OEC, #(~bmBIT6)`
553			`orl _OEA, #(bmBIT3)`
554			`clr _IOA3`
555			`setb _IOA3`
556			`anl _OEA, #(~bmBIT3)`
557
558			`mov r2, #3 // wait > 2 clocks`
559			`010008$:`
560			`mov r1, #227`
561			`010009$:`
562			`djnz r1, 010009$`
563			`djnz r2, 010008$`
564
565			`setb _IOA4`
566			`orl _OEA, #(bmBIT4)`
567			`orl _OEC, #(bmBIT6)`
568			`clr _IOC6`
569			`pop _OEB`
570			`ret`
571
572			`// size != 512`
573			`010004$:`
574			`mov _OEB,#1`
575			`010003$:`
576			`cjne r5,#0x00,010002$ // 4`
577			`cjne r6,#0x00,010002$`
578			`pop _OEB`
579			`ret`
580			`010002$: // approx 105 cycles per byte`
581			`mov C, _IOC4 // 2`
582			`mov _IOB0, C // 2`
583			`clr _IOA4 // 2`
584			`setb _IOA4 // 2`
585			`setb _IOC6 // 2`
586			`clr _IOC6 // 2`
587
588			`mov C, _IOC4`
589			`mov _IOB0, C`
590			`clr _IOA4`
591			`setb _IOA4`
592			`setb _IOC6`
593			`clr _IOC6`
594
595			`mov C, _IOC4`
596			`mov _IOB0, C`
597			`clr _IOA4`
598			`setb _IOA4`
599			`setb _IOC6`
600			`clr _IOC6`
601
602			`mov C, _IOC4`
603			`mov _IOB0, C`
604			`clr _IOA4`
605			`setb _IOA4`
606			`setb _IOC6`
607			`clr _IOC6`
608
609			`mov C, _IOC4`
610			`mov _IOB0, C`
611			`clr _IOA4`
612			`setb _IOA4`
613			`setb _IOC6`
614			`clr _IOC6`
615
616			`mov C, _IOC4`
617			`mov _IOB0, C`
618			`clr _IOA4`
619			`setb _IOA4`
620			`setb _IOC6`
621			`clr _IOC6`
622
623			`mov C, _IOC4`
624			`mov _IOB0, C`
625			`clr _IOA4`
626			`setb _IOA4`
627			`setb _IOC6`
628			`clr _IOC6`
629
630			`mov C, _IOC4`
631			`mov _IOB0, C`
632			`clr _IOA4`
633			`setb _IOA4`
634			`setb _IOC6`
635			`clr _IOC6`
636
637			`dec r5 // 1`
638			`cjne r5,#0xff,010003$ // 4`
639			`dec r6`
640			`sjmp 010003$`
641			`__endasm;`
642			`}`
643
644			`#include[ztex-fpga-flash1.h]`
645
646			`#else`
647			`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`
648			`#define[FLASH_BITSTREAM_ENABLED][0]`
649			`#endif`
650			`#endif`
651
652			`#endif /ZTEX_FPGA_H/`