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URL https://opencores.org/ocsvn/usb_fpga_2_13/usb_fpga_2_13/trunk

Subversion Repositories usb_fpga_2_13

[/] [usb_fpga_2_13/] [trunk/] [constraints/] [convert.repl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX 
PB0/FD0 PB[0]
2 
PB1/FD1 PB[1]
3 
PB2/FD2 PB[2]
4 
PB3/FD3 PB[3]
5 
PB4/FD4 PB[4]
6 
PB5/FD5 PB[5]
7 
PB6/FD6 PB[6]
8 
PB7/FD7 PB[7]
9 
 
10 
PD0/FD8         PD[0]
11 
PD1/FD9         PD[1]
12 
PD2/FD10        PD[2]
13 
PD3/FD11        PD[3]
14 
PD4/FD12        PD[4]
15 
PD5/FD13        PD[5]
16 
PD6/FD14        PD[6]
17 
PD7/FD15        PD[7]
18 
 
19 
PA0/INT0#       PA[0]
20 
PA1/INT1#       PA[1]
21 
PA2/SLOE        PA[2]
22 
PA3/WU2         PA[3]
23 
PA4/FIFOADR0    PA[4]
24 
PA5/FIFOADR1    PA[5]
25 
PA6/PKTEND      PA[6]
26 
PA7/FLAGD/SLCS# PA[7]
27 
 
28 
PC0/GPIFADR0    PC[0]
29 
PC1/GPIFADR1    PC[1]
30 
PC2/GPIFADR2    PC[2]
31 
PC3/GPIFADR3    PC[3]
32 
PC4/GPIFADR4    PC[4]
33 
PC5/GPIFADR5    PC[5]
34 
PC6/GPIFADR6    PC[6]
35 
PC7/GPIFADR7    PC[7]
36 
 
37 
PE0/T0OUT       PE[0]
38 
PE1/T1OUT       PE[1]
39 
PE2/T2OUT       PE[2]
40 
PE3/RXD0OUT     PE[3]
41 
PE4/RXD1OUT     PE[4]
42 
PE5/INT6        PE[5]
43 
PE6/T2EX        PE[6]
44 
PE7/GPIFADR8    PE[7]
45 
 
46 
RDY0/SLRD       SLRD
47 
RDY1/SLWR       SLWR
48 
RDY2    RDY2
49 
RDY3    RDY3
50 
RDY4    RDY4
51 
RDY5    RDY5
52 
 
53 
CTL0/FLAGA      FLAGA
54 
CTL1/FLAGB      FLAGB
55 
CTL2/FLAGC      FLAGC
56 
CTL3    CTL3
57 
CTL4    CTL4
58 
CTL5    CTL5
59 
 
60 
INT4    INT4
61 
INT5#   INT5_N
62 
 
63 
T0      T0
64 
 
65 
SCL     SCL
66 
SDA     SDA
67 
 
68 
RxD0    RxD0
69 
TxD0    TxD0
70 
RxD1    RxD1
71 
TxD1    TxD1

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