| 1 |
2 |
ZTEX |
NET "FXCLK" TNM_NET = "FXCLK";
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| 2 |
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TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.83333 ns HIGH 50 %;
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| 3 |
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NET "FXCLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
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| 4 |
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| 5 |
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NET "IFCLK" TNM_NET = "IFCLK";
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| 6 |
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TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
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| 7 |
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NET "IFCLK" LOC = "K20" | IOSTANDARD = LVCMOS33 ;
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| 8 |
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| 9 |
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NET "CLK" TNM_NET = "CLK";
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| 10 |
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TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
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| 11 |
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TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;
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| 12 |
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| 13 |
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NET "SLOE" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
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| 14 |
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NET "FIFOADR0" LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
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| 15 |
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NET "FIFOADR1" LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
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| 16 |
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NET "PKTEND" LOC = "AB5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6
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| 17 |
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NET "RESET_IN" LOC = "AB17" | IOSTANDARD = LVCMOS33 ; # PA7
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| 18 |
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| 19 |
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NET "PC0" LOC = "G20" | IOSTANDARD = LVCMOS33 ;
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| 20 |
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| 21 |
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NET "fd<0>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
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| 22 |
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NET "fd<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
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| 23 |
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NET "fd<2>" LOC = "W13" | IOSTANDARD = LVCMOS33 ;
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| 24 |
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NET "fd<3>" LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
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| 25 |
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NET "fd<4>" LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
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| 26 |
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NET "fd<5>" LOC = "W6" | IOSTANDARD = LVCMOS33 ;
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| 27 |
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NET "fd<6>" LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
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| 28 |
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NET "fd<7>" LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
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| 29 |
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NET "fd<8>" LOC = "V21" | IOSTANDARD = LVCMOS33 ;
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| 30 |
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NET "fd<9>" LOC = "V22" | IOSTANDARD = LVCMOS33 ;
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| 31 |
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NET "fd<10>" LOC = "U20" | IOSTANDARD = LVCMOS33 ;
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| 32 |
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NET "fd<11>" LOC = "U22" | IOSTANDARD = LVCMOS33 ;
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| 33 |
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NET "fd<12>" LOC = "R20" | IOSTANDARD = LVCMOS33 ;
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| 34 |
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NET "fd<13>" LOC = "R22" | IOSTANDARD = LVCMOS33 ;
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| 35 |
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NET "fd<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
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| 36 |
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NET "fd<15>" LOC = "P19" | IOSTANDARD = LVCMOS33 ;
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| 37 |
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| 38 |
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NET "FLAGB" LOC = "F19" | IOSTANDARD = LVCMOS33 ;
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| 39 |
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| 40 |
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NET "SLRD" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
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| 41 |
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NET "SLWR" LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
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| 42 |
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| 43 |
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| 44 |
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############################################################################
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| 45 |
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# VCC AUX VOLTAGE
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| 46 |
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############################################################################
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| 47 |
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CONFIG VCCAUX=2.5;
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| 48 |
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| 49 |
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############################################################################
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| 50 |
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## Memory Controller 3
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| 51 |
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## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT
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| 52 |
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## Frequency: 200 MHz
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| 53 |
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## Time Period: 5000 ps
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| 54 |
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## Supported Part Numbers: MT46V32M16BN-5B-IT
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| 55 |
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############################################################################
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| 56 |
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CONFIG MCB_PERFORMANCE= EXTENDED;
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| 57 |
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| 58 |
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############################################################################
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| 59 |
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## I/O TERMINATION
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| 60 |
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############################################################################
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| 61 |
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#NET "mcb3_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
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| 62 |
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#NET "mcb3_dram_dqs" IN_TERM = UNTUNED_SPLIT_50;
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| 63 |
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#NET "mcb3_dram_dqs_n" IN_TERM = UNTUNED_SPLIT_50;
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| 64 |
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#NET "mcb3_dram_udqs" IN_TERM = UNTUNED_SPLIT_50;
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| 65 |
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#NET "mcb3_dram_udqs_n" IN_TERM = UNTUNED_SPLIT_50;
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| 66 |
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NET "mcb3_dram_dq[*]" IN_TERM = NONE;
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| 67 |
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NET "mcb3_dram_dqs" IN_TERM = NONE;
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| 68 |
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NET "mcb3_dram_dqs_n" IN_TERM = NONE;
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| 69 |
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NET "mcb3_dram_udqs" IN_TERM = NONE;
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| 70 |
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NET "mcb3_dram_udqs_n" IN_TERM = NONE;
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| 71 |
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| 72 |
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#NET "mcb3_dram_dq[*]" OUT_TERM = UNTUNED_50;
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| 73 |
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NET "mcb3_dram_a[*]" OUT_TERM = UNTUNED_50;
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| 74 |
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NET "mcb3_dram_ba[*]" OUT_TERM = UNTUNED_50;
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| 75 |
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NET "mcb3_dram_ck" OUT_TERM = UNTUNED_50;
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| 76 |
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NET "mcb3_dram_ck_n" OUT_TERM = UNTUNED_50;
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| 77 |
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NET "mcb3_dram_cke" OUT_TERM = UNTUNED_50;
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| 78 |
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NET "mcb3_dram_ras_n" OUT_TERM = UNTUNED_50;
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| 79 |
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NET "mcb3_dram_cas_n" OUT_TERM = UNTUNED_50;
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| 80 |
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NET "mcb3_dram_we_n" OUT_TERM = UNTUNED_50;
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| 81 |
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#NET "mcb3_dram_odt" OUT_TERM = UNTUNED_50;
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| 82 |
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NET "mcb3_dram_dm" OUT_TERM = UNTUNED_50;
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| 83 |
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NET "mcb3_dram_udm" OUT_TERM = UNTUNED_50;
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| 84 |
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| 85 |
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############################################################################
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| 86 |
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# I/O STANDARDS
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| 87 |
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############################################################################
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| 88 |
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NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II;
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| 89 |
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NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II;
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| 90 |
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NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II;
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| 91 |
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NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II;
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| 92 |
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NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II;
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| 93 |
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NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II;
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| 94 |
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NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II;
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| 95 |
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NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II;
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| 96 |
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NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II;
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| 97 |
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NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II;
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| 98 |
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NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II;
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| 99 |
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NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II;
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| 100 |
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NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II;
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| 101 |
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#NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II;
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| 102 |
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NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II;
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| 103 |
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NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II;
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| 104 |
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NET "mcb3_rzq" IOSTANDARD = SSTL18_II;
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| 105 |
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NET "mcb3_zio" IOSTANDARD = SSTL18_II;
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| 106 |
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| 107 |
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############################################################################
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| 108 |
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# MCB 3
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| 109 |
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# Pin Location Constraints for Clock, Masks, Address, and Controls
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############################################################################
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| 111 |
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NET "mcb3_dram_a[0]" LOC = "M5" ;
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| 112 |
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NET "mcb3_dram_a[10]" LOC = "K6" ;
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| 113 |
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NET "mcb3_dram_a[11]" LOC = "B1" ;
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| 114 |
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NET "mcb3_dram_a[12]" LOC = "J4" ;
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| 115 |
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NET "mcb3_dram_a[1]" LOC = "L4" ;
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| 116 |
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NET "mcb3_dram_a[2]" LOC = "K3" ;
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| 117 |
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NET "mcb3_dram_a[3]" LOC = "M4" ;
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| 118 |
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NET "mcb3_dram_a[4]" LOC = "K5" ;
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| 119 |
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NET "mcb3_dram_a[5]" LOC = "G3" ;
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| 120 |
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NET "mcb3_dram_a[6]" LOC = "G1" ;
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| 121 |
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NET "mcb3_dram_a[7]" LOC = "K4" ;
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| 122 |
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NET "mcb3_dram_a[8]" LOC = "C3" ;
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| 123 |
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NET "mcb3_dram_a[9]" LOC = "C1" ;
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| 124 |
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NET "mcb3_dram_ba[0]" LOC = "E3" ;
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| 125 |
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NET "mcb3_dram_ba[1]" LOC = "E1" ;
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| 126 |
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NET "mcb3_dram_ba[2]" LOC = "D1" ;
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| 127 |
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NET "mcb3_dram_cas_n" LOC = "P3" ;
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| 128 |
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NET "mcb3_dram_ck" LOC = "F2" ;
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| 129 |
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NET "mcb3_dram_ck_n" LOC = "F1" ;
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| 130 |
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NET "mcb3_dram_cke" LOC = "J6" ;
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| 131 |
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NET "mcb3_dram_dm" LOC = "H1" ;
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| 132 |
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NET "mcb3_dram_dq[0]" LOC = "N3" ;
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| 133 |
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NET "mcb3_dram_dq[10]" LOC = "R3" ;
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| 134 |
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NET "mcb3_dram_dq[11]" LOC = "R1" ;
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| 135 |
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NET "mcb3_dram_dq[12]" LOC = "U3" ;
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| 136 |
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NET "mcb3_dram_dq[13]" LOC = "U1" ;
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| 137 |
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NET "mcb3_dram_dq[14]" LOC = "V2" ;
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| 138 |
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NET "mcb3_dram_dq[15]" LOC = "V1" ;
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| 139 |
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NET "mcb3_dram_dq[1]" LOC = "N1" ;
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| 140 |
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NET "mcb3_dram_dq[2]" LOC = "M2" ;
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| 141 |
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NET "mcb3_dram_dq[3]" LOC = "M1" ;
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| 142 |
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NET "mcb3_dram_dq[4]" LOC = "J3" ;
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| 143 |
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NET "mcb3_dram_dq[5]" LOC = "J1" ;
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| 144 |
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NET "mcb3_dram_dq[6]" LOC = "K2" ;
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| 145 |
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NET "mcb3_dram_dq[7]" LOC = "K1" ;
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| 146 |
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NET "mcb3_dram_dq[8]" LOC = "P2" ;
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| 147 |
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NET "mcb3_dram_dq[9]" LOC = "P1" ;
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| 148 |
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NET "mcb3_dram_dqs" LOC = "L3" ;
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| 149 |
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NET "mcb3_dram_dqs_n" LOC = "L1" ;
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| 150 |
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#NET "mcb3_dram_odt" LOC = "M3" ;
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| 151 |
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NET "mcb3_dram_ras_n" LOC = "N4" ;
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| 152 |
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NET "mcb3_dram_udm" LOC = "H2" ;
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| 153 |
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NET "mcb3_dram_udqs" LOC = "T2" ;
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| 154 |
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NET "mcb3_dram_udqs_n" LOC = "T1" ;
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| 155 |
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NET "mcb3_dram_we_n" LOC = "D2" ;
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| 156 |
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| 157 |
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# The following pins are available for used as RZQ or ZIO pins#
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| 158 |
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NET "mcb3_rzq" LOC = "AA2" ;
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| 159 |
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NET "mcb3_zio" LOC = "Y2" ;
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