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URL https://opencores.org/ocsvn/usb_fpga_2_13/usb_fpga_2_13/trunk

Subversion Repositories usb_fpga_2_13

[/] [usb_fpga_2_13/] [trunk/] [examples/] [usb-fpga-1.15y/] [ucecho/] [fpga/] [ucecho.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX
NET "CLK" TNM_NET = "CLK";
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TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
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NET "CLK"  LOC = "L22" | IOSTANDARD = LVCMOS33 ;
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NET "CS"  LOC = "AB11" | IOSTANDARD = LVCMOS33 ;
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NET "pb<0>"  LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
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NET "pb<1>"  LOC = "V13" | IOSTANDARD = LVCMOS33 ;
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NET "pb<2>"  LOC = "W13" | IOSTANDARD = LVCMOS33 ;
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NET "pb<3>"  LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
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NET "pb<4>"  LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
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NET "pb<5>"  LOC = "W6" | IOSTANDARD = LVCMOS33 ;
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NET "pb<6>"  LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
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NET "pb<7>"  LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
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NET "pc<0>"  LOC = "G20" | IOSTANDARD = LVCMOS33 ;
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NET "pc<1>"  LOC = "T20" | IOSTANDARD = LVCMOS33 ;
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NET "pc<2>"  LOC = "Y5" | IOSTANDARD = LVCMOS33 ;
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NET "pc<3>"  LOC = "AB9" | IOSTANDARD = LVCMOS33 ;
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NET "pc<4>"  LOC = "G19" | IOSTANDARD = LVCMOS33 ;
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NET "pc<5>"  LOC = "H20" | IOSTANDARD = LVCMOS33 ;
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NET "pc<6>"  LOC = "H19" | IOSTANDARD = LVCMOS33 ;
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NET "pc<7>"  LOC = "H18" | IOSTANDARD = LVCMOS33 ;
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# NET "SCL" LOC = "F22" | IOSTANDARD = LVCMOS33 ;
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# NET "SDA" LOC = "E22" | IOSTANDARD = LVCMOS33 ;
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