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[/] [usb_fpga_2_13/] [trunk/] [examples/] [usb-fpga-2.13/] [2.13c/] [memfifo/] [fpga/] [memfifo.xdc] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX 
# fxclk_in
2 
create_clock -period 20.833 -name fxclk_in [get_ports fxclk_in]
3 
set_property PACKAGE_PIN P15 [get_ports fxclk_in]
4 
set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
5 
 
6 
# IFCLK
7 
create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]
8 
#create_clock -name ifclk_in -period 33.333 [get_ports ifclk_in]
9 
set_property PACKAGE_PIN P17 [get_ports ifclk_in]
10 
set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
11 
 
12 
# source mode pins
13 
set_property PACKAGE_PIN R15 [get_ports {mode[0]}]              ;# PA0/INT0#
14 
set_property PACKAGE_PIN T15 [get_ports {mode[1]}]              ;# PA1/INT1#
15 
set_property IOSTANDARD LVCMOS33 [get_ports {mode[*]}]
16 
set_property PULLUP true [get_ports {mode[*]}]
17 
 
18 
# PA7/FLAGD/SLCS#
19 
set_property PACKAGE_PIN T10 [get_ports reset]
20 
set_property IOSTANDARD LVCMOS33 [get_ports reset]
21 
 
22 
# PB[0..9], PD[0..7]
23 
set_property PACKAGE_PIN M16 [get_ports {fd[0]}]
24 
set_property PACKAGE_PIN L16 [get_ports {fd[1]}]
25 
set_property PACKAGE_PIN L14 [get_ports {fd[2]}]
26 
set_property PACKAGE_PIN M14 [get_ports {fd[3]}]
27 
set_property PACKAGE_PIN L18 [get_ports {fd[4]}]
28 
set_property PACKAGE_PIN M18 [get_ports {fd[5]}]
29 
set_property PACKAGE_PIN R12 [get_ports {fd[6]}]
30 
set_property PACKAGE_PIN R13 [get_ports {fd[7]}]
31 
set_property PACKAGE_PIN T9 [get_ports {fd[8]}]
32 
set_property PACKAGE_PIN V10 [get_ports {fd[9]}]
33 
set_property PACKAGE_PIN U11 [get_ports {fd[10]}]
34 
set_property PACKAGE_PIN V11 [get_ports {fd[11]}]
35 
set_property PACKAGE_PIN V12 [get_ports {fd[12]}]
36 
set_property PACKAGE_PIN U13 [get_ports {fd[13]}]
37 
set_property PACKAGE_PIN U14 [get_ports {fd[14]}]
38 
set_property PACKAGE_PIN V14 [get_ports {fd[15]}]
39 
set_property IOSTANDARD LVCMOS33 [get_ports {fd[*]}]
40 
set_property DRIVE 4 [get_ports {fd[*]}]
41 
 
42 
# CTL0/FLAGA
43 
set_property PACKAGE_PIN N16 [get_ports {FLAGA}]
44 
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]
45 
 
46 
# CTL1/FLAGB
47 
set_property PACKAGE_PIN N15 [get_ports FLAGB]
48 
set_property IOSTANDARD LVCMOS33 [get_ports FLAGB]
49 
 
50 
# PA2/SLOE
51 
set_property PACKAGE_PIN T14 [get_ports SLOE]
52 
set_property IOSTANDARD LVCMOS33 [get_ports SLOE]
53 
 
54 
# PA4/FIFOADR0
55 
set_property PACKAGE_PIN R11 [get_ports FIFOADDR0]
56 
set_property IOSTANDARD LVCMOS33 [get_ports FIFOADDR0]
57 
 
58 
# PA5/FIFOADR1
59 
set_property PACKAGE_PIN T11 [get_ports FIFOADDR1]
60 
set_property IOSTANDARD LVCMOS33 [get_ports FIFOADDR1]
61 
 
62 
# PA6/PKTEND
63 
set_property PACKAGE_PIN R10 [get_ports PKTEND]
64 
set_property IOSTANDARD LVCMOS33 [get_ports PKTEND]
65 
 
66 
# RDY0/SLRD
67 
set_property PACKAGE_PIN V16 [get_ports SLRD]
68 
set_property IOSTANDARD LVCMOS33 [get_ports SLRD]
69 
 
70 
# RDY1/SLWR
71 
set_property PACKAGE_PIN U16 [get_ports SLWR]
72 
set_property IOSTANDARD LVCMOS33 [get_ports SLWR]
73 
#set_property DRIVE 4 [get_ports SLWR]
74 
#set_property SLEW FAST [get_ports SLWR]
75 
 
76 
# I/O delays
77 
set_input_delay -clock ifclk_in -min 0 [get_ports {FLAG* fd[*]}]
78 
set_input_delay -clock ifclk_in -max 15 [get_ports {FLAG* fd[*]}]
79 
set_output_delay -clock ifclk_in -min 0 [get_ports {SLRD SLWR}]
80 
set_output_delay -clock ifclk_in -max 15 [get_ports {SLRD SLWR}]
81 
 
82 
# LED's
83 
set_property PACKAGE_PIN H15 [get_ports {led1[0]}]              ;# A6 / B21~IO_L21P_T3_DQS_16
84 
set_property PACKAGE_PIN J13 [get_ports {led1[1]}]              ;# B6 / A21~IO_L21N_T3_DQS_16
85 
set_property PACKAGE_PIN J14 [get_ports {led1[2]}]              ;# A7 / D20~IO_L19P_T3_16
86 
set_property PACKAGE_PIN H14 [get_ports {led1[3]}]              ;# B7 / C20~IO_L19N_T3_VREF_16
87 
set_property PACKAGE_PIN H17 [get_ports {led1[4]}]              ;# A8 / B20~IO_L16P_T2_16
88 
set_property PACKAGE_PIN G14 [get_ports {led1[5]}]              ;# B8 / A20~IO_L16N_T2_16
89 
set_property PACKAGE_PIN G17 [get_ports {led1[6]}]              ;# A9 / C19~IO_L13N_T2_MRCC_16
90 
set_property PACKAGE_PIN G16 [get_ports {led1[7]}]              ;# B9 / A19~IO_L17N_T2_16
91 
set_property PACKAGE_PIN G18 [get_ports {led1[8]}]              ;# A10 / C18~IO_L13P_T2_MRCC_16
92 
set_property PACKAGE_PIN H16 [get_ports {led1[9]}]              ;# B10 / A18~IO_L17P_T2_16
93 
set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}]
94 
set_property DRIVE 12 [get_ports {led1[*]}]
95 
 
96 
set_property PACKAGE_PIN U9 [get_ports {led2[0]}]               ;# C3 / AB17~IO_L2N_T0_13
97 
set_property PACKAGE_PIN V9 [get_ports {led2[1]}]               ;# D3 / AB16~IO_L2P_T0_13
98 
set_property PACKAGE_PIN U8 [get_ports {led2[2]}]               ;# C4 / Y16~IO_L1P_T0_13
99 
set_property PACKAGE_PIN V7 [get_ports {led2[3]}]               ;# D4 / AA16~IO_L1N_T0_13
100 
set_property PACKAGE_PIN U7 [get_ports {led2[4]}]               ;# C5 / AA15~IO_L4P_T0_13
101 
set_property PACKAGE_PIN V6 [get_ports {led2[5]}]               ;# D5 / AB15~IO_L4N_T0_13
102 
set_property PACKAGE_PIN U6 [get_ports {led2[6]}]               ;# C6 / Y13~IO_L5P_T0_13
103 
set_property PACKAGE_PIN V5 [get_ports {led2[7]}]               ;# D6 / AA14~IO_L5N_T0_13
104 
set_property PACKAGE_PIN T8 [get_ports {led2[8]}]               ;# C7 / W14~IO_L6P_T0_13
105 
set_property PACKAGE_PIN V4 [get_ports {led2[9]}]               ;# D7 / Y14~IO_L6N_T0_VREF_13
106 
set_property PACKAGE_PIN R8 [get_ports {led2[10]}]              ;# C8 / AA13~IO_L3P_T0_DQS_13
107 
set_property PACKAGE_PIN T5 [get_ports {led2[11]}]              ;# D8 / AB13~IO_L3N_T0_DQS_13
108 
set_property PACKAGE_PIN R7 [get_ports {led2[12]}]              ;# C9 / AB12~IO_L7N_T1_13
109 
set_property PACKAGE_PIN T4 [get_ports {led2[13]}]              ;# D9 / AB11~IO_L7P_T1_13
110 
set_property PACKAGE_PIN T6 [get_ports {led2[14]}]              ;# C10 / W12~IO_L12N_T1_MRCC_13
111 
set_property PACKAGE_PIN U4 [get_ports {led2[15]}]              ;# D10 / W11~IO_L12P_T1_MRCC_13
112 
set_property PACKAGE_PIN R6 [get_ports {led2[16]}]              ;# C11 / AA11~IO_L9N_T1_DQS_13
113 
set_property PACKAGE_PIN U3 [get_ports {led2[17]}]              ;# D11 / AA10~IO_L9P_T1_DQS_13
114 
set_property PACKAGE_PIN R5 [get_ports {led2[18]}]              ;# C12 / AA9~IO_L8P_T1_13
115 
set_property PACKAGE_PIN V1 [get_ports {led2[19]}]              ;# D12 / AB10~IO_L8N_T1_13
116 
set_property IOSTANDARD LVCMOS33 [get_ports {led2[*]}]
117 
set_property DRIVE 12 [get_ports {led2[*]}]
118 
 
119 
# switches
120 
#set_property PACKAGE_PIN F18 [get_ports SW7]           ;# A11 / B18~IO_L11N_T1_SRCC_16
121 
set_property PACKAGE_PIN F16 [get_ports SW8]            ;# B11 / D17~IO_L12P_T1_MRCC_16
122 
#set_property PACKAGE_PIN E18 [get_ports SW9]           ;# A12 / B17~IO_L11P_T1_SRCC_16
123 
set_property PACKAGE_PIN F15 [get_ports SW10]           ;# B12 / C17~IO_L12N_T1_MRCC_16
124 
set_property IOSTANDARD LVCMOS33 [get_ports {SW*}]
125 
set_property PULLUP true [get_ports {SW*}]
126 
 
127 
# location constraints
128 
set_property LOC PLLE2_ADV_X1Y1 [get_cells dram_fifo_inst/dram_fifo_pll_inst]
129 
 
130 
# TIG's
131 
set_false_path -from [get_clocks *ifclk_out] -to [get_clocks *clk200]
132 
set_false_path -from [get_clocks *ifclk_out] -to [get_clocks ]
133 
set_false_path -from [get_clocks *clk_pll_i] -to [get_clocks *ifclk_out]
134 
 
135 
# bitstream settings
136 
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
137 
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
138 
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
139 
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
140 
 

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