Subversion Repositories usb_fpga_2_13

intraffic

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This example shows how the EZ-USB input FIFO interface is used.

A traffic generator sends test data to the EZ-USB. The hosts PC reads

out this data and verifies it.

The traffic generator is implemented in the FPGA and supports two modes:

1. (IOA3=0) This mode supports data flow control using FIFO full flag

   (FLAGB) and SLWR control pin. Use this mode as starting point for

   data acquisition applications.

2. (IOA=3) In this mode and uninterrupted test pattern is generated,

   i.e. flow control is disabled. This mode is used for performance

   measurements (speed rate and interrupt measurements)